technology III-V MOSFETs
?Traditional? approaches will not succeed – experiments and simulations reveal that contact resistance rises rapidly when the contact size enters the nanoscale. Several groups have recently developed different approaches for overcoming this problem, including those from Glasgow, which has turned to NiInAs to fabricate an ultra-low resistance, shallow, metallic source-drain. According to Thayne, this is the first source-drain technology that can meet the most aggressive ITRS specification for the 12 nm technology node, which corresponds to a gate pitch of 27 nm.
Figure 3.A sulphidation process developed by researchers at the Tyndall Institute can offset most of the degradation in mobility resulting from the removal of an arsenic cap. This is a promising result for non-planar transistors,which will not have pristine interfaces
Intel’s move from planar transistors to three-dimensional points the way to production of non-planar devices, which will not have pristine interfaces. To consider the implications of this trend, Thayne, in partnership with Paul McIntyre at Stanford and Paul Hurley at the Tyndall Institute, have looked at the impact of various treatments of transistor performance. The team compared three wafers. Two of them were removed from MBE chamber the after the growth of III-V materials: A gate dielectric was added to one wafer without any intermediate surface treatment, so air-exposed oxides were likely to be present in the dielectric-semiconductor interface; and a optimised sulphidation treatment was applied to the other prior to deposition of the high-k dielectric. The third wafer had as arsenic cap deposited in the MBE chamber to prevent oxidation in air. This cap was removed in the atomic layer deposition tool at Stanford, enabling the gate deposition on a pristine surface. Looking at the mobility of MOSFETs made from these wafers reveals that it is possible to produce interfaces as good as those on pristine surfaces, if a sulphidation process is performed (see Figure 3).
The second issue that Thayne and his co-workers have investigated is the fabrication of low resistance source and drain contacts with dimensions of just a few nanometres. The ITRS roadmap dictates that as gate pitch is reduced from 75 nm in 2011 to just 15 nm in 2024, source and drain contacts must be trimmed from 21 nm to 2 nm, while source and drain resistances are cut from 160 øµm to 110 øµm.
The third strand of research at the Nanoelectronics Research Centre has been the development of approaches for forming fully self-aligned III-V MOSFETs with silicon compatible process flows. The team has pioneered two different designs: ‘Gate first’ and ‘replacement gate’ architectures. The former has been used to form In0.3Ga0.7As flatband MOSFETs with a GaO/GaGdO dielectric stack and a 100 nm gate length. These transistors exhibit a peak drain current of 250 µA/µm, transconductance of 150 µS/µm and a sub-threshold swing of 150 mV/decade. Sub- threshold swing falls to 130 mV/decade with the replacement gate architecture, which has a modest on-state performance due to a very high access resistance of 18 køµm. This issue can be addressed by improving the source drain anneal, which is needed to supress material diffusion in very small devices.
Figure
4.According to Peided Ye from Purdue University,III-V MOSFETs have evolved from planar structures to those that wrap a dielectric right around the channel
The second issue that Thayne and his co-workers have investigated is the
fabrication of low resistance source and drain contacts with dimensions of just a few nanometres. The ITRS roadmap dictates that as gate pitch is reduced from 75 nm in 2011 to just 15 nm in 2024
28
www.compoundsemiconductor.net June 2012
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84 |
Page 85 |
Page 86 |
Page 87 |
Page 88 |
Page 89 |
Page 90 |
Page 91 |
Page 92 |
Page 93 |
Page 94 |
Page 95 |
Page 96 |
Page 97 |
Page 98 |
Page 99 |
Page 100 |
Page 101 |
Page 102 |
Page 103 |
Page 104 |
Page 105