technology III-V MOSFETs
carriers are injected with a higher velocity, thanks to their higher energy; and due to superior mobility, these materials can trim access resistance and thereby boost the efficiency of gate modulation.
Material attributes Developers of III-V MOSFETs must select a material that combines a high carrier velocity with the potential to yield a device with a low operating voltage. According to Thayne, as gate pitch decreases from 75 nm to 15 nm, the value expected in 2024, channel concentration may decrease from 8.5 x 1012 cm-2 to 5.1 x 1012 cm-2 while the carrier velocity will increase from 1.3 x 105 ms-1 to 3.5 x 105 ms-1. The most promising materials for meeting those requirements are alloys of InGaAs, and work from MIT suggest that In0.7Ga0.3As channels can produce injection velocities above 3 x 105 ms-1 at gate lengths below 20 nm.
Thayne also discussed additional requirements for the introduction of III-V MOSFETs for logic applications. He said that transistors will need to have a sub-threshold swing of 75 mV/decade, so that they could be turned-off easily, and they will probably need to be built with a non-planar architecture, such as the ‘Ivy Gate’ tri-gate structure employed by Intel for the manufacturing of transistors at the 22 nm node. In addition, due to scaling, source and drain dimensions will have to be just a few nanometres, which could lead to an unwanted hike in contact resistance.
The Glasgow team, which has been involved in both the European Dual Logic program and efforts led by the Semiconductor Research Corporation Non-Classical CMOS Research Center, has focused its efforts in three directions: Gate stack improvements, resolving issues related to the scaling of source and drain contacts, and the development of silicon compatible process flows for III-V MOSFETs.
Efforts have centred on a flatband architecture MOSFET (see Figure 2). This is similar to a HEMT, according to Thayne, because there is delta-doping in a high bandgap material, leading to the transfer of electrons to a low bandgap channel where they create a high-mobility, two-dimensional electron gas. If a high work- function gate metal is formed on top of the dielectric, depletion occurs, driving the device into an off-state at zero bias. Forward biasing of the gate repopulates the channel with carriers.
This MOSFET architecture is claimed to have two key strengths: Immunity to short-channel effects, due to a high bandgap lower barrier; and high mobility, thanks to a combination of no doping in the channel, low interface roughness scattering and a low resistance of
Figure 2.Ian Thayne’s group at the University of Glasgow,UK, has developed III-V MOSFETs with a flatband architecture
the source and drain extension access regions. When the team started developing III-V MOSFETs at the beginning of the previous decade, efforts were partly devoted to establishing a good gate stack. Initially they employed a Veeco Gen III dual chamber MBE system to grow III-V layers by MBE on a semi-insulating GaAs substrate, before transferring the sample under vacuum to a second chamber, where they added a Ga20 template and a GdGaO layer. The flatband III-V MOSFETs fabricated from these wafers produced mobilities in excess of 5000 cm2 V-1s-1 at sheet carrier densities above 2 x 1012 cm-2, and transistors with a 1 µm gate length had a transconductance of 357 µS/µm and a sub- threshold swing of 68 mV/decade.
To increase injection velocity, the researchers switched to In0.53Ga0.47As channels and Al2O3 dielectrics, which were deposited by a 60-cycle atomic layer deposition process. The benefits of this new structure included gains in mobility – at an electron density of 2 x 1012 cm-2, mobility topped 6000 cm2 V-1s-1.
For surface-channel transistors with a 1 µm gate and a 2.5 nm-thick Al2O3 dielectric, transconductance hit 432 µS/µm, but the sub- threshold swing reached 150 mV/decade.
June 2012
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