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December, 2011 High Performance Probe Sockets By Ila Pal, Ironwood Electronics, Burnsville, MN
processor and memory has driven the industry to embrace 3D packaging solutions. 3D packaging can be achieved by die stacking in one pack- age, package-in-a-package stacking or package-on-package stacking. Each method has its advantages and disad- vantages. Package-on-package stack-
T
he evolution of cell phones to today’s high-end smart phones with a multi-core applications
quired by today’s consumer de mands, IC engineers have been adding more features to their 2nd generation processor, while the memory perform- ance is increased by faster communi- cations with the processor. Faced with such a high level of
complexity, test engineers need a socket which can test the 1st genera- tion processor and memory. We have seen many product offerings for this
the test engineer uses a memory probe in between the memory and processor to verify the performance of the newer memory. A typical four-level interconnect
will enable the development se quence of 3D ICs. De sign ing a socket to accommodate these variations en - counters many challenges. There are two major challenges to be ad dres sed: force and alignment.
Force Challenges The most difficult of all chal-
Typical four-level interconnect enabling development sequence of 3D ICs.
ing, which has been evolved into a variety of formats, enables stacking of packages from different suppliers and mixed IC technologies. It also allows for burn-in and testing before the actu- al stacking is performed. In a typically stacked package,
the bottom package is the processor and the top package is memory. Be - cause of additional applications re -
one level stacked socket. In order to move from 1st generation to 2nd gen- eration devices, a test engineer needs a 2, 3, or 4 level stacked socket. During the development phase, the test engineer needs to use a processor probe in between the processor and the main development board to con- nect with a logic analyzer to perform the signal capability functions. Then
lenge is force balancing. In a simple case, the processor has 515 solder balls and the PoP (Package on Package) memory has 168 sol- der balls. The memory, with its 168 balls, requires 5-lbs. of force for optimum compression that results in less than 20 milliohms of contact resistance per ball. The processor, with 515 balls, requires 15-lbs. of force for opti- mum compression, resulting in less than 20 milliohms of contact resistance per ball. In order to balance the force at each level, another 10-lbs. of force is needed at the memory level. This will balance the force at processor level. When 15-lbs. of force is applied to the memory with only 168 balls, the elastomer under- neath memory will be over-com- pressed. In addition, there is the potential danger of memory device warpage due to this high force. To counterbalance, a sheet of rubber whose thickness can fill the gap between bottom side of memory device and top side of elastomer inter- face is used. This rubber can absorb the extra 10-lbs. of force resulting in only the recommended force on the elastomer section that has been inter- faced with the memory device. Similar force balancing has to be per- formed at each level of interconnec- tion if there is a force variation.
Probe Socket Configurations The actual measurements are
addressed by a recently introduced series of high-performance BGA sockets for high-speed probing of the memory chip and processor debug- ging during the design phase. The customer can use this stacked socket to probe a 1GB mem-
Bottom to Top Stack up
C8453 C9133
C9666 C10015 C10040* C10062
BGA841, 12x12mm, 0.4mm pitch, 29x29 full array
BGA664, 12x12mm, 0.57mm interstitial pitch, 20x20 partial array
BGA619, 12x12mm, 0.4mm pitch, 28x28 partial array
BGA520, 12x12mm, 0.4mm pitch, 29x29 partial array
* To be used with other Probe Sockets
Table 1: Off-the-shelf probe sockets compatible with Agilent’s memory probe.
Continued on next page
BGA841, 12x12mm, 0.4mm pitch, 29x29 full array
N/A
BGA168, 12x12mm, 0.5mm pitch, 23x23 partial array
BGA168, 12x12mm, 0.5mm pitch, 23x23 partial array
BGA168, 12x12mm, 0.5mm pitch, 23x23 partial array
BGA216, 12x12mm, 0.4mm pitch, 29x29 partial array
N/A
BGA168, 12x12mm, 0.5mm pitch, 23x23 partial array
Target PCB > Elastomer > Processor > Elastomer > Memory probe with memory soldered
Target PCB > Elastomer > Memory Probe > Elastomer > Memory
Target PCB > Elastomer > Processor Probe with Processor soldered > Elastomer > Memory
Target PCB > Elastomer > Processor > Spring Pin > Memory probe > Elastomer > Memory
Target PCB > Elastomer > Processor
Target PCB > Spring Pin > Processor > Spring Pin > Memory Probe > Spring Pin > Memory
ory device using Agilent’s Flex Probe stacked inside the socket. Agilent’s probe makes contact with the target PCB through the 0.5mm thick high density elastomer contact. The mem- ory chip sits on top of the probe and makes contact with it using high- speed elastomer contacts. The Agilent probe brings the signals out to oscilloscope/logic analyzer for high-speed probing. If an available configuration is
not suitable, the first step in procur- ing a custom probe socket is to com- municate the device specifications to Ironwood Electronics. An application engineer will be assigned to meet
Alignment plate Solder ball PCB pad
A = Ball diameter B = Hole to edge of alignment plate C = Hole to PCB pad D = PCB pad to PCB pad E = Ball to Ball F = Edge of ball to edge of alignment plate
Typical variations in XY direction for a single stack up interconnect.
Elastomer is the “interconnect” used in this stack up.
this request, and will work with the customer’s design engineer to pro- duce a custom probe socket drawing that shows footprint and stack-up information. A proposal will be sent to the customer after acceptance of the custom probe socket drawing. The company provides various
options such as first article, delivery schedule and quantity price break- downs. At the start of the project, an application and design engineering team will work on the new project and will keep the customer updated on schedules and project milestones.
Alignment Challenges Similar to force balancing,
alignment level challenges have been addressed at each interconnection level. Let us consider a simple case where a test engineer needs to test the processor only. It is a simple one-
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