Vendor View
Fig. 10 – Variation of dopant concentrations at different points in the MOCVD Chamber
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absorption coefficient, is capable of receiving n- type and p-type dopants and can be integrated into low cost, large scale manufacturing processes. The areas for improvement of CdTe thin film PV are cell and module efficiencies.
Fig. 13 – WLI pseudo colour height map of the pad feature
Surface Metrology Surface Metrology is the quantitative characterisation of the topography of surfaces. Semiconductor devices are complex architectural systems where physical dimension and chemical composition combine to produce the desired performance characteristics of the device. A range of techniques are available including SEM, Field Emission SEM, Atomic Force Microscopy (AFM), Scanning Profilometry and White Light Interferometry (WLI).
Fig. 12 – WLI image of the device feature
The SEM techniques provide visual information on surface features with lateral resolution down to a few nm. However, there is no clear topographical information conveyed in the SEM images, as shown in the image of a device area (Fig. 11 – field of view ~100µm). In contrast, the WLI image from a similar
Fig. 14 – Line profile of the pad feature taken from the line shown in Fig. 13
Fig. 11 – Scanning Electron Microscopy (SEM) image of device area (field of view ~100Ìm)
device area (Fig. 12) clearly shows the topographic detail in 3D false colour representation. The storage of x, y and z (height) information at each pixel point in the image set allows detailed analysis of topographical information from the sampled area. For example, roughness parameters including Sa – the mean surface roughness, may be calculated for any defined area of a device or wafer surface. So the effect of processing steps such as plasma or chemical etching on a semiconductor substrate can be easily assessed and quantified. The line profile across the pad feature shows a centre-pad height of ~2.5µm with side walls 1.5µm higher and a FWHM of ~88µm. This article illustrates the benefits of using a range of modern surface characterisation techniques to obtain quantitative chemical and physical information on the structure and composition of semiconductor materials. These techniques provide the ability to detect chemical species with sub-ppb sensitivity and to measure surface features on the nm scale. This knowledge is critical to process engineers, designers and failure analysts to optimise yields, reduce failure rates and improve device design.
www.euroasiasemiconductor.com Issue IV 2010
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