Semiconductor Characterization
A comparison of the 2-D maps shown in Figures 7b and 7c,
as well as 1-D profiles shown in Figures 8 and 9, demonstrate a qualitative agreement between SCM and electron holography. Both line profiles provide clear delineation of the p/n junction, as well as good contrast of dopant concentration and type. A minor difference at the P- region of the waveguide is observed. Te electron holography map (Figure 7b) shows a slight shiſt toward n-type electrostatic potential at the bottom part of the P- region of the waveguide, while no shiſt is observed in the SCM map (Figure 7c) at the same location. Tis shiſt observed in electron holography could be due to charge at the bottom interface between Si/SiO2
. Holography junction profiles of a negative field-effect
transistor (NFET) device with <100> channel orientation. In a regular complementary metal-oxide-semiconductor (CMOS), the channel direction is normally along the <110> direction. However, based on band structure calculation, a higher p-FET drive current exists (high mobility) along the <100>. Terefore, in some applications, the <100> junction of Si is used. Because of that, the junction profile for a <100> channel device is of interest in semiconductor development and manufacturing. Te advantage of analyzing a <100> channel device is that the tilt angle to off-zone in the TEM is quite small, ∼0.2o
, compared to >1–2o angle required for ana-
lyzing a <110> channel device. Tis allows reduction of the projection effects in junction profile imaging due to sample tilt. Terefore, high spatial resolution in the junction profile is achievable. Figure 10 shows a junction profile for a NFET where
n-type source-drains and source/drain extension (SDE) regions are represented by red; p-type channel and p-well regions are represented by blue and green, respectively. In the map, the slightly blue color just below the gate indicates that the region has higher p-type active dopant concentration than the green region near the bottom edge of the image. Te over- lap of n-type SDE with the gate is clearly visible. SDE overlap with the gate provides the critical overlap capacitance (COV) necessary for optimum n-type metal-oxide-semiconductor (NMOS) device operation. Too much overlap leads to devices with source-drain (SD) leakage, and no overlap leads to a higher threshold voltage and lower drive current. Optimizing COV is critical for semiconductor device performance and manufacturing yield. SSRM junction profile measurements of a positive field-
effect transistor (PFET) device. High spatial resolution 2-D junction mapping of a PFET device fabricated in silicon-on- insulator (SOI) is discussed in [20]. Figure 11a shows a dark- field scanning transmission electron microscope (STEM) image of a PFET device with embedded-SiGe (eSiGe) in the source and drain regions. Two layers of e-SiGe, shown as light contrast in the image, consist of a thinner U-shaped buffer and the main SiGe layer that fills the U-shaped buffer layer. A channel SiGe (c-SiGe) layer used for work function adjustment is shown as a lighter contrast under the gate. Te buried oxide is shown as a dark region along the bottom of the image. Fig- ure 11b shows a spreading resistance image, with brown rep- resenting lower resistance, whereas yellow represents higher resistance regions. Low resistances are observed in the deep p+ source/drain, SDE (source-drain extension), NiSi contact
2021 May •
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Figure 10: Junction profile of a <100> orientation complementary metal- oxide-semiconductor (CMOS) NFET device with 1 nm fringe spacing.
Figure 11: (a) Dark field STEM image showing e-SiGe and c-SiGe 22 nm SOI PFET devices; (b) spreading resistance image shows p+ deep SD, SDE, NiSi and gate in brown color that represent lower resistance, and low-doped n-Well in yellow color to represent higher resistance.
regions, and gate stack. Te dashed line illustrates the junc- tion boundary between p+ SD, SDE, and n-well. In Si and SiGe regions, high resistance represents low carrier concentrations,
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