Column: JESD204 standard
change the link operation within the confines of the converter or FPGA architecture:
(1)
where M is the number of converters on the link, N’ is the number of informational bits sent in a sample (including sample resolution, control and tail bits), fs
is the device or sample
Figure 3: An ADC application layer can re-map five 12-bit ADC samples into the space used by four JESD204B N’ = 16 samples
Q: How are tail bits used in JESD204B and what is their purpose? A: Te JESD204B link allows for more information space to be allotted than actually needed, to send the converter data and control bits. If data for a particular converter or configuration does not fill up the entire space, then this padding is filled with so-called tail bits. Take, for example, a case where a space of N’ = 16 is more than the parceled 13 bits of real data (N = 13 + CS = 0). Tree tail bits will fill the unused data space; see Figure 2. Tail bits are informationless dummy bits, used to pad the unused transmitter space. Since they have the potential to cause unwanted spurious noise if they are assigned a recurring static value, they also can be optionally represented as a pseudorandom sequence. Both the transmitter and receiver must understand that these bits are informationless, based on the link configuration. Te receiver can therefore simply discard them from the stream of relevant data.
Q: My link patterns work fine, but I am not getting converter data transmitted in a normal operating mode. In past converter generations, low-voltage differential signalling (LVDS) and parallel interfaces allowed easy probing/debugging of a least significant bit (LSB) or most significant bit (MSB) pin of a DAC/ADC to see if the functional converter operation was taking place. How can I probe an MSB or LSB when using the JESD204B interface? A: Tis is one of the few drawbacks to
the JESD204B interface. It is not easy to electrically probe an LSB or MSB I/O to see if there is correct activity to and from the converter, because the sample data is serialised per channel, so a particular weighted bit cannot easily be probed electrically. However, a few options can be used to debug a system issue when you quickly want to know what, if any, valid data is being sent or received from your converter. Some oscilloscope vendors provide
real-time data processing to serially decode 8b/10b data and display an unencoded stream on the oscilloscope screen. Unscrambled data can be probed in this fashion to determine what activity is taking place on the link. FPGA vendors offer an internal probing
soſtware tool that gives system designers a method to observe the I/O data sent and received from within the FPGA, by connecting it via a USB dongle to a computer. Also, some ASICs and converters offer an internal serial loop-back self-test mode that can help decipher data issues on the link.
Q: How do I calculate the lane rate for my converter with the link’s other parameters? A: System designers using JESD204B can easily compute the number of lanes or lane rate for their link given that they know the other key criteria of their converter, ASIC or FPGA. Tere is a mathematical relationship for all the basic link parameters, such that one unknown variable can be determined and solved. Based on the result, system designers can choose other parameters to
12 December 2021/January 2022
www.electronicsworld.co.uk
clock; L is the lane count; lane rate is the bit rate for a single lane; and 10 ⁄ 8 is the link overhead due to 8b ⁄ 10b encoding. For example, consider a dual ADC with = 235MHz, using two lanes:
N’ = 16, fs (2)
Q: What is an application layer in JESD204B and what does it do? A: An application layer is a method provided for in JESD204B that allows sample data to be mapped outside the normal specification. Tis can be useful for certain converter modes that need to pass data samples in sizes that are relatively different from the N’ of the link. An otherwise inefficient arrangement on
the link can be made more efficient with a lower lane count or lower lane speed by using an application layer. Both the transmitter and receiver need to be configured to understand a specific application layer, as it can be customised or uniquely designed by a particular converter mode. Figure 3 shows an example where five samples are partitioned into a space typically occupied by only four. When using Equation 1 for application
layer calculations, the effective N’, instead of the actual N’, must be used. For example, in the application layer case shown in Equation 3, although the actual JESD024B sample N’ is 16, the effective N’ for ADC samples can be figured since 64 bits are used to send five samples. Terefore, Neff
= 64/5 =
12.8. With all other variables held equal, the lane rate could then be 20% slower:
(3)
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