Column: JESD204 standard
allowing the link I/O to be reconfigured in the best order for easiest PCB layout. Te FPGA receiver can take the same initial configuration data and change the expected lane assignments to recover the data. With this ability, the routing of lanes from one device to the other can be made much easier and independent of the initial named assignment by the silicon vendor in the data sheet.
Q: I want to design a converter into my system that uses a JESD204B multipoint link. How is this different from a single link? A: Te JESD204B specification makes provisions for what is known as a “multipoint link interface”, a communications link that connects three or more JESD204B devices. Tis link configuration can make sense over a single link in some cases, depending on how the converter is being used. Take for example a dual ADC that uses
JESD204B. In most cases, a dual ADC would have a single clock input to both converters. Tis would force simultaneous analogue sampling at the same frequency. But for some unique applications, such a device could also use two separate input clocks, with each clock driving its respective ADC independently. Tis allows for a sampling phase difference between the two ADCs, or even for each ADC to be sampled with a non-coherent frequency with respect to the other. In the latter case, a single JESD204B link with data from both converters would not operate correctly without a complex back-end FIFO scheme. A solution could be to have the dual
converter use a multipoint link JESD204B interface, with each channel using its own serial link output. Noncoherent clocks could then be used on each ADC, and each serial link output could easily route independently to a separate FGPA or ASIC. A multipoint link configuration can also be used when sending multiple streams of data from a single FPGA to several DACs. Device clock distribution skew can be more challenging to minimise within a multipoint configuration as the number of devices within the link grows.
With the link
configuration data, a multiple-lane transmitter can easily reassign any digital logical serial data to any physical output lane using a crossbar mux,
allowing the link I/O to be reconfigured in the best order for easiest PCB layout
Q: Is the deterministic latency within JESD204B the same as the total latency of my converter? A: Te total latency of an ADC is the time it takes an analogue sample to be clocked in, processed and output digitally from the device. Similarly, the total latency of a DAC is the time from when the digital sample data is clocked into the part until that corresponding sample is clocked out of the analogue output. Typically, these are both measured in sample clock periods of resolution, since they are frequency- dependent. Tis is fundamentally not the same definition as the deterministic latency described by a JESD204B link implementation. Deterministic latency across the JESD204B
link is defined by the time it takes data to propagate from the parallel framed data input at the transmitter (ADC or source FPGA) to the parallel deframed data output at the receiver (DAC or receiver FPGA). Tis time is typically measured in either frame clock periods of resolution or device clocks; see Figure 1. Te definition excludes the analogue front-end core of an ADC and the back-end analogue core of a DAC. Not only are two devices a function in this latency computation, but so is the serial data signal routing interfacing the two. Tis means that the deterministic latency could be larger or smaller within a multi-converter system or multipoint link, depending on the length of the JESD204B lane routing. Receiver buffer delays can help account for latency differences due to routing.
Figure 2: Three tail bits can be used to pad and fill a second octet for N' = 16 when a converter only uses 13 bits of sample data
www.electronicsworld.co.uk December 2021/January 2022 11
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