Column: JESD204 standard
Common design
questions about working with the JESD204B interface
By Ian Beavers, Product Engineering Manager, Automation Energy and Sensors Team, Analog Devices
T
he JESD204B serial data link interface was developed to support the growing bandwidth needs of higher-speed converters. A third-generation standard,
it provides a higher maximum lane rate (up to 12.5Gbps per channel) while supporting deterministic latency and harmonic frame clocking. Additionally, it now can easily move large quantities of data for processing by taking advantage of higher-performance converters that are compatible and scaleable with open-market FPGA solutions. FPGA providers have talked about
multi-gigabit serialisation/de-serialisation (SERDES) interfaces for many years. In the past though, most analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs) were not configured with these high-speed serial interfaces. Te FPGAs and the converters did not interface with any common standard that took advantage of the high SERDES bandwidth. JESD204B-compliant converters can solve this problem, but this new capability introduces some questions.
8b/10b encoding Tere can be no assurance of a DC-balanced signal on a differential channel with random unencoded serial data, as there easily could be more ones or zeros transmitted to one than the other. Random data sent across a serial link also has the potential for long periods of inactivity or data that could be all ones or all zeros for a relatively long time. When this happens, DC balancing of an unencoded serial data stream becomes
railed to one extreme or the other, so that when active data begins again, there is a strong potential for bit errors as the biasing of the lines is restarted. An additional long-term concern is electromigration, as a differential DC voltage is maintained on one side of the pair relative to the other. To address these issues, an 8b/10b encoding scheme is commonly used in differential serial data streams, including JESD204B. In 8b/10b encoding, 10 bits are used to
send the original 8 bits of information from the source transmitter via a lookup table. Tis results in a 25% inefficiency overhead (10b/8b = 1.25). In addition, the encoding allows for at least three-bit but no more than eight-bit transitions per 10-bit symbol. Tis ensures that there are enough transitions for the receiver to recover an embedded clock, regardless of the dynamic activity of the underlying data. Te disparity between the number of
binary zeros and ones in the serial stream is kept to within ±1 using 8b/10b encoding, so the signal maintains a DC balance over time. Te converse decoding of 10 bits to 8 bits must then be performed on the data stream at the receive end to be able to recover the original data using the reverse lookup table. A more efficient 64b/66b encoding that operates on a similar principle, but with only a small overhead, is more advanced and has the potential to be used in future generations of JESD204.
Figure 1: A conceptual example of JESD204B deterministic latency between framer and deframer on two linked devices. The latency is a function of three items: the transmitter, the receiver and the interface propagation time between the two
Q: Te assigned JESD204B lanes of my converter do not route easily to my FPGA on the system board. Tere are crisscrossing pairs all over, susceptible to crosstalk. Can I re-map the JESD204B lanes to make the layout easier? A: Although converters may have JESD204B serial lanes defined by a number, letter or other nomenclature to designate their particular relevance in the complete link, they are not required to be fixed. Te specification allows re- mapping of these assignments in the initial configuration data, as long as each lane and device has a unique identification. With the link configuration data, a multiple-lane transmitter can easily re- assign any digital logical serial data to any physical output lane using a crossbar mux,
10 December 2021/January 2022
www.electronicsworld.co.uk
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