electronica 2018
Effective measures to defeat warpage problem for PCBs
Nowadays, electronic products call for miniaturisation and high accuracy so that component miniaturisation has become an essential development trend. When miniaturised components are ready to be assembled on large-area PCBs, much higher requirement has to be laid to board smoothness. Naturally, it has become an essential topic for PCB manufacturers to consider how to reduce warpage extent of PCBs. Dora Yang, technical engineer from PCBCart, tells us more
A
ccording to manufacturing regulations confirmed by IPC-600, the warpage of PCBs that are ready to go through SMT
assembly is required to be 0.75 per cent at most. When it comes to small component assembly on circuit boards with large areas, however, that regulation fails to work. Generally speaking, to meet the demands of miniaturised components assembly on PCB boards with large areas, PCB warpage should be reduced to 0.5 per cent or lower. Warpage analysis Warpage problem will be analysed first in this article with a sample 8-layer PCB whose size is 248mm±0.25×162.2±0.20. The warpage of this board is required to be 0.5 per cent but its practical warpage after the first batch of production falls into the range from 2.5 per cent to 3.2 per cent. The layer structure of an 8-layer PCB is demonstrated in Figure 1.
Copper residue ratio for each layer is demonstrated as Figure 2. Based on the above analysis, the
protruding characteristic of this sample board is uneven copper distribution of each layer. Moreover, copper is relatively thick. As a result, board warpage is aroused. Solutions to defeat PCB warpage Firstly, the primary method to balance copper residue between layers of the board lies in adding copper pouring in blank. To reduce deformation stress of the board, it’s an
agreeable idea to shrink panel size with a rotation panelisation method. When it comes to this sample PCB, panel size should be modified from 610mm×520mm to 610mm×356mm. Panel array of the former is 3×2 while that of the latter is 2×2. Due to the above measures for improvement,
copper residue ratio is demonstrated in Figure 3. After such modifications, warpage modified to be in the range from 2.0 per cent to 2.9 per cent that receives obvious improvement but it’s a little far from the requirement of 0.5 per cent.
Based on the first solution, board rigidity is added. The implementation of this makes PCB warpage in the range from 2.0 per cent to 2.9 per cent. Evidently, this scheme doesn’t work on warpage issue solving, indicating that there’s little correlation between warpage and board rigidity. We need to go on optimising scheme 1, that is, searching for more ways on copper residue balance.
Based on scheme 1, Layer 2 and Layer 6 should be exchanged with each other. In accordance with this, PCB warpage remains within 0.5 per cent and it still remains at 0.5 per cent even after twice reflow soldering, which is compatible with requirement. Furthermore, a trial
production of 300 pieces verifies the reliability of this scheme. As a result, this scheme performs best among all the schemes. According to above experiments, since the distribution among all dielectric layers is even, it’s uneven distribution of copper that leads PCB warpage to occur. Through balancing copper residue on each layer of PCB board, board warpage reduces from the range from 2.5 per cent to 3.2 per cent to the range within 0.5 per cent, indicating that the core solution for PCB warpage issue lies in balance on copper residue between dielectric layers and copper layers. Accordingly, as far as warpage is concerned during assembly process, equalisation should be achieved by component layout, thermal distribution and assembly distribution so that board warpage can be decreased with product quality guaranteed.
www.pcbcart.com
CIE electronica 2018
9
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