EDA


target described in the processor description language. Once hotspots are identifi ed, they can be addressed by adding custom instructions to the target core. The modifi ed core can be analysed with application software and the design process continued iteratively if needed.


When the core design is stable, then the final software toolchain, RTL & UVM environment can be generated. As a final stage the RTL can be verified against the golden instruction accurate reference model. Studio also provides automation to assist the processor verification including consistency checks and random assembler program generation.


Processor design automation is moving from an obscure niche or semiconductor design to the mainstream. It is a key enabler for more processing performance in a time of failing semiconductor scaling.


Fig 3. Example of processor design automation: Codasip Studio www.codasip.com


Unfortunately, if the core is described in an HDL the SW toolchain needs to be manually updated separately from the HDL. If, however, the core is described in a processor description language (such as Codasip’s CodAL) everything needed for generating


the RTL, software toolchain and verifi cation environment is available. The fi nal enabler for DSA design is a processor design automation tool such as Codasip’s Studio. Such a tool can take a processor core described or customised using a


processor description language and generate the HW and SW representations of the core. Such tools start with profi ling the software that needs to run on the processor core to identify performance hotspots. The tools can use a candidate RISC-V core as a


References 1


John L. Hennessy & David A. Patterson, “A New Golden Age for Computer Architecture”, Communications of the ACM, February 2019, Vol. 62 No. 2, Pages 48-60


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Components in Electronics


July/August 2022 29


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