Feature: Interconnections
chips in new form factors, without signifi cant tradeoff s.
Hybrid bonding and AI T is rising interest in AI across nearly every vertical segment of the global digital economy will cause a surge in demand for hybrid bonding technology across the semiconductor industry, too. Hybrid bonding is a direct bonding
Hybrid bonding technology meets AI in the semiconductor industry
By Dr. Seung Kang, Vice President of Strategy, Adeia T
he rapid rise of new artifi cial intelligence (AI) applications, recently boosted by broad interest in generative AI (GenAI), has now also caught the
attention of the semiconductor industry.
Growing semiconductor demands AI demands high compute capacity, which outpaces the current capabilities of semiconductor technologies. Market analyst house Gartner states that semiconductors designed to execute AI workloads will experience double-digit growth over the next few years, increasing nearly 26% in 2024 to over $67bn, reaching $119.4bn by 2027. AI is dramatically impacting the
semiconductor industry because it accelerates the need for increasingly powerful and energy-effi cient computing systems, surpassing the capabilities of incumbent semiconductor platforms.
Being computationally intensive, AI workloads require semiconductor systems to perform massive parallel computing. Currently, the key drivers of such systems are a graphics processing unit (GPU) and high-bandwidth memory (HBM), integrated with high-speed interconnects. To meet state-of-the-art AI system
requirements, unprecedented performance benchmarks are needed. T is is especially true when dealing with large language models. However, both processors and memory components face fundamental semiconductor scaling challenges. GPUs and AI-customised neural
processors rely on cutting-edge logic nodes that off er a smaller footprint, lower power consumption and faster speed. As the demand for computing performance continues to grow, building such processors on a monolithic chip – even the most advanced processing node – becomes challenging. In such cases, the desired approach is to disaggregate and reassemble
24 July/August 2024
www.electronicsworld.co.uk
technology that interconnects wafer and wafer, die and wafer and die and die at an ultra-fi ne pitch without requiring solder or other adhesives. It is a method of interconnecting semiconductor wafers or dies by combining metal-to-metal and dielectric-to-dielectric bonding. It is commonly associated with Direct Bond Interconnect (DBI and DBI Ultra). Today, hybrid bonding fi nds applications in 3D heterogeneous integration scenarios, where diff erent types of chips (designed for diff erent functions or from diff erent suppliers) are seamlessly integrated and interoperable. T e evolving requirements of AI systems are expected to surpass the capabilities of conventional semiconductor system architectures. T is trend is driving the industry towards adopting disaggregated multi-chip confi gurations. Hybrid bonding is well-positioned as a compelling technology to underpin and facilitate these innovative semiconductor architectures and there is growing consensus across the industry that hybrid bonding technology will become widely adopted, both for processors and HBMs. Compared with other methods, hybrid bonding off ers inherent advantages in high- density I/O, reduced parasitic delay, shorter height and improved thermal performance. Adeia has consistently been at the forefront
of hybrid bonding technology. In 2015, we acquired intellectual property rights to hybrid bonding technology through the acquisition of Ziptronix, one of the original founders of hybrid bonding, and have since maintained our commitment to advance innovation in this space. We not only license our comprehensive
hybrid bonding portfolio to various semiconductor markets, including memory, logic, RF and image sensor, but also provide support to partners through technology transfers.
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