Feature: T&M
Figure 5: LTC6373 driving ADAQ4003 (gain = 0.454, 2MSPS)
Figure 6: SNR vs LTC6373 gain settings, with the LTC6373 driving ADAQ4003 (gain = 0.454, 2MSPS)
A 10µF capacitor on the REF pin is critical to helping replenish the charge of an internal capacitive DAC during the bit decision process, and vital to achieving peak conversion performance. With the inclusion of the reference buffer, the user can implement a much lower power reference source than many traditional SAR-ADC-based signal chains, because the reference source drives a high-impedance node instead of the dynamic load of the SAR capacitor array. Te user has the flexibility to choose the reference buffer input voltage that matches the desired analogue input range.
Easy PCB layout Te 7mm × 7mm BGA package of the ADAQ4003 offers at least a four times footprint reduction compared to a traditional discrete signal chain (Figure 3), for smaller instruments without sacrificing performance.
Figure 7: THD vs LTC6373 gain settings, with the LTC6373 driving ADAQ4003 (gain = 0.454, 2MSPS)
Te PCB layout is critical in preserving signal integrity and
achieving the expected performance from the signal chain. Te pinout of the ADAQ4003 eases the layout and allows designers to keep the analogue and digital sections separate and confined to certain areas, to mitigate radiating noise. Te ADAQ4003 incorporates all the necessary low equivalent
series resistance (ESR) and low equivalent series inductance (ESL) decoupling ceramic capacitors for the reference (REF) and power supply pins, VS
+, VS -, VDD and VIO . Tese capacitors provide a low
impedance path to ground at high frequencies to handle transient currents. No external decoupling capacitors are required, and there
is no known performance impact or any EMI issue in their absence. Tis performance impact was verified on the ADAQ4003
www.electronicsworld.co.uk December/January 2023 29
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