Feature: T&M
resistor (RG1). Not only that, the gain error driſt is also influenced by a choice of resistor type such as a thin-film, low-temperature- coefficient resistor, whilst sourcing matched resistors is challenging amid cost and board space constraints. In addition, the generation of odd, bipolar supplies is
inconvenient for many designers due to the extra cost and real estate constraints on their PCBs. Designers also need to carefully select the optimal passive
components, including an RC low-pass filter (which is placed between the ADC driver output and the ADC inputs), as well as a decoupling capacitor for the successive approximation register (SAR) ADC dynamic reference node. An RC filter helps limit the noise at the ADC inputs and reduces the effect of kickbacks coming from the capacitive DAC input of a SAR ADC. C0G- or NP0-type capacitors and reasonable value of series resistance should be chosen to keep the amplifier stable and limit its output current. Finally, the PCB layout is extremely critical for preserving signal integrity and achieving the expected performance from the signal chain.
Figure 3: Size comparison of the ADAQ4003 µModule device vs a discrete signal chain solution
Easing the design journey Many system designers end up implementing different signal chain architectures for the same applications. However, one size does not fit all, so Analog Devices (ADI) has focused on common sections of signal chain, signal conditioning and digitisation to solve system designers’ major pain points. ADI’s µModule solutions provide a more complete signal chain with advanced performance, to bridge a gap between standard discrete components and highly-integrated customer-specific ICs. Te ADAQ4003 is a SiP solution that offers the best balance between R&D cost and form-factor reduction whilst accelerating time to prototype. Tis µModule incorporates multiple common signal processing, conditioning blocks and critical passive components, as well as an FDA, a stable reference buffer and an 18-bit, 2MSPS, SAR ADC. Te module simplifies signal chain design and the development cycle of a precision measurement system by transferring component selection, optimisation and layout from the designer to the device itself, and solves the design challenges discussed earlier. Te precision resistor array around the FDA is built with ADI’s
Figure 4: An ADAQ4003 FFT with shorted inputs, with the performance unchanged before and after removing the external decoupling capacitors for various rails
are not equal, any imbalance in output amplitude or phase produces an undesirable common-mode component in the output that is amplified by its noise gain and causes a redundant noise and offset in the differential output of the FDA. Terefore, it’s imperative that the ratio of gain/feedback resistors matches well. In other words, the combination of input source impedance and RG2
(RG1 ) should
match (that is, β1 = β2) to avoid signal distortion and mismatch in the common-mode voltage of each output signal, and to prevent the increase in common-mode noise coming from the FDA. One of the ways to counterbalance differential offset and avoid output distortion is to add an external resistor in series with the gain
28 December/January 2023
www.electronicsworld.co.uk
iPassives technology, which addresses circuit imbalance, reduces parasitics, achieves gain matching up to 0.005%, and optimises driſt performance (1ppm/°C). It also minimises temperature- dependent errors and reduces system-level calibration burdens. Te FDA’s fast settling and wide common-mode input range, along with configurable gain options (0.45, 0.52, 0.9, 1 or 1.9), allow gain and attenuation adjustments and a fully-differential or single- ended-to-differential input. Te ADAQ4003 includes a single-pole RC filter between the
ADC and its driver, designed to maximise settling time and input signal bandwidth. All the necessary decoupling capacitors for the voltage reference node and power supplies are also included, simplifying the bill of materials. In addition, the ADAQ4003 houses a reference buffer configured at
unity gain to optimally drive the dynamic input impedance of the SAR ADC reference node and the corresponding decoupling capacitor.
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