search.noResults

search.searching

saml.title
dataCollection.invalidEmail
note.createNoteMessage

search.noResults

search.searching

orderForm.title

orderForm.productCode
orderForm.description
orderForm.quantity
orderForm.itemPrice
orderForm.price
orderForm.totalPrice
orderForm.deliveryDetails.billingAddress
orderForm.deliveryDetails.deliveryAddress
orderForm.noItems
Feature: T&M


verify their functionality as the control of R&D budgets and time-to-market become challenging. Heterogeneous integration via system-in-package (SiP) technology continues to lead key trends within the industry, including the move to higher density, increased functionality, enhanced performance and longer mean- time-to-failure. Hence, there are ways to leverage heterogeneous integration that will deliver precision conversion and provide a solution for a significant application impact.


Test and


measurement requires high- accuracy and high-precision data acquisition solutions


By Maithil Pachchigar, System Applications Engineer, Analog Devices


S


ystem architects and circuit-level hardware designers spend significant research and development resources to develop high- performance, discrete linear and precision signal chain blocks for their end applications, such as test and measurement, industrial


automation, healthcare and aerospace and defence, for example. The solutions measure and protect, condition and acquire, or synthesize and drive. But, the electronic industry’s dynamics are fast evolving and there is less time to build and prototype analogue circuits to


26 December/January 2023 www.electronicsworld.co.uk


System designers to the task System designers face logistical challenges such as component selection and design optimisation for final prototypes, and technical challenges such as driving ADC inputs and protecting them from overvoltage events, minimising power needs and achieving higher system throughput with low-power microcontrollers and digital isolators. With increased focus on system soſtware and applications to differentiate their system solution, OEMs are assigning more resources to soſtware development instead of hardware development. Tis is resulting in increased pressure on hardware development to minimise design iterations. System designers developing data acquisition signal chains


typically require high input impedance to allow direct interface with various sensors, which could have varying common-mode voltages and unipolar or bipolar single-ended or differential-input signals present; see Figure 1. Let’s take a holistic view of the typical signal chain (Figure 2)


implemented using discrete components, to understand some of the system designer’s major challenges. Te key portion of the precision data acquisition subsystem is shown in Figure 2, where the 20Vp-p


output of the instrumentation amplifier is applied to


the non-inverting input of a fully-differential amplifier (FDA). Te FDA provides the necessary signal conditioning, including level shiſting, attenuating the signal and setting the output swing between 0V and 5V with a 2.5V common mode, opposite in phase, resulting in a 10Vp-p


differential signal to the ADC inputs


to maximise its dynamic range. Te in-amp is powered with dual supplies of ±15V, whereas the FDA is powered from +5V/–1V, and the ADC is powered from a 5V supply. Te ratio of feedback resistors (RF1


= RF2 ) to gain resistors (RG1 = RG2 at 0.5. Te noise gain (NG) of the FDA is defined as:


) sets the FDA gain


where β1 and β2 are feedback factors:


Here we will present how the circuit imbalance (that is, β1 ≠ β2) or mismatch in feedback and gain resistors (RG1


RF1 , RF2


, RG2


, ) around the FDA influences key specifications such as


SNR, distortion, linearity, gain error, driſt and input common- mode rejection ratio (CMRR). Te differential output voltage of the FDA depends on VOCM


, so when feedback factors β1 and β2


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52