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New SOI-based Process Platform for Complex MEMS Devices


Introduction Silicon-on-insulator (SOI) based MEMS processes have demonstrated impressive usage growth in recent years. Compared to surface micro machining on polysilicon fabrication, SOI processes have the added benefit of smoother surfaces and sidewalls, as well as lower issues related to reduced residual stress in the silicon. These are essential material characteristics for many MEMS applications targeting high yield, including optical MEMS devices for display and telecommunications. Micralyne recently developed a SOI-based MEMS process platform, MicraGEM-Si, and has made this process available to companies and researchers as part of a cost effective Multi-Project Wafer (MPW) prototyping service through a partnership with CMC Microsystems. This platform is ideal to develop devices such as micro mirrors, optical switches, resonators, inertial and biosensors.

Platform Technology The new process platform provides the following features: • Two thick SOI structure layers with up to three functional levels of silicon.

• Top device layer with silicon etch in the back side as well as a release etch from the top side which enables low stiffness springs and flat large mirror plate with low mass.

• Deep etch features on the upper and lower devices layers are precisely aligned with enough accuracy to enable vertical comb drive actuators.

• Upper and lower devices layers are connected electrically through the bond interface allowing 3D routing of electrical signals.

• Patterned low-stress gold metallisation on the top surface is suited for highly reflective mirrors and contact pads for gold wire bonding.

This technology platform includes a combination of established MEMS processes, designed to enable a wide variety of structures and is ideal for fabricating vertical comb drive actuators which are essential for advanced optical MEMS micro mirrors, which in turn enable variable optical attenuators (VOA), multichannel switches and wavelength selective switch (WSS) modules.

Key steps within the process include high aspect ratio Deep Reactive Ion Etch (DRIE), non-contact stepper photolithography, aligned wafer-to-wafer bonding and low stress mirror metallisation. Stepper lithography provides non-contact exposures with excellent repeatability, consistency, alignment accuracy, throughput and quality. It has been demonstrated that silicon fingers can be precisely aligned in a staggered pattern when using 3D wafer-to-wafer bonding. With thoughtful process design, out-of-plane features can be aligned to within 0.4 μm overlay tolerance.

Step 2: Define and Etch Top SOI Wafer Backside The Top SOI wafer is patterned and etched to a depth of 20 μm. Once the Top SOI wafer is bonded and the handle wafer is removed, this will leave a suspended region of silicon with a 10 μm thickness.

Fabrication Flow

Step 1:Define Trench 1, Trench 2 and Trench 3 on Base Wafer The device layer thickness of the Base wafer is 50 μm. The regions defined as Trench 1 are etched to a final depth of 50 μm (all the way through the device layer). Trench 2 regions are etched to a final depth of 35 μm, leaving a 15 μm high section of silicon sitting on the buried oxide of the Base SOI. Trench 3 regions are etched to a final depth of 10 μm, leaving a silicon region with a height of 40 μm above the Base SOI. With these three regions, many complex 3D silicon structures can be created, including cavities, electrodes and wires for electrical routing, as well as lower combs for vertical comb drive actuators.

<< Figure 1: Process flow. >>

42 | commercial micro manufacturing international Vol 7 No.3

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