Strain gage testing: the delta effect of thermal cycle testing
as well as process related stress and strain large stiffening effect on a circuit card, will and losses in future revenue. To this
due to manufacturing processes as well as location wise, and thus strain pathways are end, companies are performing accelerated
environmental forces such as CTE move- created around these components, which life testing of the electronic hardware to de-
ment and strain pathways over temperature then creates high strain levels on certain termine the weak link in their designs and
cycling. other components in that strain pathway component bill of material. Also the ability
Component suppliers and final end or corridor. CTE movement of these mate- to understand strain and strain pathways
use customers are starting to set limits on rial sets used on the assembly play a large on electronic hardware is the analytical
the amount of strain and strain rate levels role in the applied stress being localized at tool of choice to validate component place-
seen on their components and final assem- certain locations on the board. Strain due ment location on the electronic circuit
blies. This action is placing emphasis back to environmental forces combined with board assembly. Microstrain and its cor-
onto the designer and process engineer natural CTE movement can cause prema- responding time duration on the board at
to understand their processes and part ture failure during the operating thermal the component lead interconnect interface
location to insure that products meet their cycles of an assembly. The review looks at to the board is the silent killer of electronic
warranty and useful life periods. With this the effect of CTE movement and strain hardware failures.
renewed interest and emphasis comes the in-parted from burn in and/or accelerated Because fractures cannot be seen read-
need for the industry to determine limits life cycling to determine the weak link in ily and they can occur in such short time
and test protocols that are standardized to the overall design of the system. The use durations on multiple occasions, frac-
insure repeatability and consistency from of the mathematical formula Y-X or X-Y to tures can be an invisible and silent killer
manufacturer to end user. IPC/JDEC 9704 determine the peak-to-peak amplitude and of solder joint interconnections at the
STANDARD is the industry standard that its corresponding delta difference from component level to board surface interface.
was released in 2005 to address standard- tension-to-compression or vice-versa is the Fractures manifest themselves as an inter-
ization of strain gage testing. The challenge essential information needed to determine mittent failure initially but ultimately go
is in finding and setting the strain limits impact over time. The ability to capture to a full open state when the component
so that your design and component set are these data sets is essential to understand- fractures completely at its interconnection
not jeopardized by elevated microstrain ing where the greatest strain is located and interface from lead to board level pad
levels. Life cycle testing shows the amount its corresponding pathway. Also essential surface (Figure 1). All component device
of strain being applied during temperature is the dwell or duration of stress over time packages are susceptible from the smallest
cycling and the forces behind CTE fatigue which can be the silent killer in some chip passive devices all the all the way up
fractures and strain pathway forces. The applications because it is time dependent. the packaging curve to the very large active
issue is long term reliability of finished This model is best used with a tempera- device packages; QFPs, BGAs (standard
assemblies in their operating environment ture / time profile analysis overlaid with and micro), QFNs as well as Gull and
and their ability to withstand the environ- the strain gage data to capture time and J-leaded devices. Some component package
mental forces. temperature effects of CTE movement types are more susceptible than others,
STI’s Analytical Lab has taken a lead and strain levels on certain component such as the larger and higher I/O devices
role in strain gage testing and data evalu- locations. such as BGAs (Figure 2), QFPs and the new
ation of applied strain and strain rate on QFN style packages. But one should not
printed circuit card assemblies. STI has Background be fooled into a false sense of security with
also spent considerable time evaluating Strain gage testing is being more widely component package types that are more
the effects of strain pathways due to the used to understand the invisible and silent robust to applied forces because strain and
natural stiffening of certain areas of the killer of electronic hardware. Military, strain time duration are the key ingredients
card due to connector placement, large automotive, high-end commercial, medi- to latent defects over time at the solder
component packages, heat sink attachment cal, and industrial applications are being interconnect interface to the PCB (printed
devices, and other encapsulating material environmentally tested in special acceler- circuit board) card pad surface interface.
sets. These types of components have a ated life tests to determine statistically the The real culprit is the strain and strain du-
life and warranty ration time that can be applied from CTE
Location A Location B
periods. Return (coefficient of thermal expansion) caused
rates and warranty by temperature cycling in the fielded state.
X-axis Y-axis X-axis Y-axis
work has a huge This is why one performs accelerated life
-200 -786 -573 -851 impact on overall testing on designed systems to determine
*See Chart A for raw data support, see red highlights
profitability and the weak link in the electronic hardware.
premature failure Strain gage testing captures and quantifies
Table 1. Maximum microstrain seen during thermal cycling.
causes customer ill the microstrain forces as well as the time
Location A Location B
Location A Location B
X-axis Y-axis X-axis Y-axis
X-axis Y-axis X-axis Y-axis
-36˚C/-200 103˚C/-786 -40˚C/-573 105˚C/-851
-36˚C/-200 103˚C/-786 -40˚C/-573 105˚C/-851
85˚C/-1 -36˚C/659 105˚C/-232 -36˚C/192
85˚C/-1 -36˚C/659 105˚C/-232 -36˚C/192
*See Chart A for raw data support, see red highlights
-199 1445 -351 1043
Table 2. Maximum and minimum strain level recorded according to Table 3. Maximum to minimum strain level delta swing recorded according
temperature cycle. to temperature cycle.
www.globalsmt.net Global SMT & Packaging – February 2009 – 11
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