FEATURE MEMS DESIGN
Reliable chip-size MEMS packaging
Gregory Flinn from SCHOTT explores how HermeS glass wafers with hermetically sealed solid Through Glass Vias‹ (TGV) are enabling fully gastight and robust long-term enclosures with electrical connections in and out of MEMS devices
n meeting the requirements for environmental hermeticity while still having electrical access to the outside world, microelectronics systems often rely upon Through Silicon Via (TSV) and ceramic solutions as an approach to packaging. Packaging of such systems must in general consider many aspects of the proposed application, including target cost, manufacturing process practicalities, operator convenience and protection from environmental concerns. However, each of the aforementioned packaging technologies only partially satisfies the full complement of ideal specifications. The situation for MEMS-enabled devices
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and sensors is more stringent still. MEMS packaging must also protect the often minute structures against the harshest and varied of chemical, thermal and mechanical environments, while at the same time providing a reliable interface to the next level in the packaging hierarchy, and still also allowing cost-effective fabrication. For these reasons, and also to satisfy the drive to provide greater device yield per wafer, we see an increasing trend towards wafer-level packaging (WLP) approaches that make wire bonding processes obsolete. In directly addressing the needs for WLP, glass specialist SCHOTT is offering HermeS glass substrates, with solid and hermetically- sealed Through Glass Vias(TGVs) (Fig. 1). These glass wafers satisfy a significantly larger suite of the wafer-level packaging goals for MEMS as compared to other ‘through via’ approaches.
HERMES THROUGH GLASS VIAS SCHOTT is naturally well known for its vast experience with glass. In extension to this, the company's Electronic Packaging division also has over 70 years of experience with hermetic glass-to-metal seals. Realisation of the shortcomings of existing
wafer-level through via packaging approaches for MEMS led the company to develop an alternative. The result of this development, HermeS glass wafers, combines the superior material characteristics of glass (compared to silicon or ceramics) together with embedded and hermetically-sealed solid metal vias. The advantages of this combination as a
22 SPRING 2015 | MICROMATTERS
environments, so too for medical sensors in terms of resistance to bodily fluids and repeated sterilisation cycles. Furthermore, the low dielectric constant of
glass means excellent RF properties, while highly conductive via materials such as tungsten enable high-performance electrical and thermal pathways to the PCB – packaging with HermeS wafers thus also provides excellent radio-frequency (RF) performance. For RF-enabled MEMS devices this translates into improved power efficiency, greater bandwidth and better environmental isolation in a simplified hermetic package. Compare these qualities with similar approaches in silicon or ceramics, and the benefits are obvious across the board: better material integrity, improved via reliability, superior thermal performance, greater RF performance, enhanced electrical isolation, better flexibility and superior WLP capability.
REDUCING DIE SIZE IN A WAFER-LEVEL One important step on the roadmap for MEMS packaging is a reduction in device footprint. Lithography masks are expensive, so if yield per wafer can be improved by increasing the number of devices per wafer, development costs can be recouped more easily. Current packaging integrates an ASIC next to
component of a WLP solution are manifold. The application-relevant material characteristics of glass, such as high mechanical, thermal and chemical resistance, provide obvious benefits in any packaging solution. Two of the three glass types available for HermeS are also thermally matched to silicon, so thermal sensitivity can thus be minimised further. Notably, the embedded metal vias are introduced into the glass during melting, so they become physically and chemically bonded to the glass. And lastly, HermeS glass wafers are compatible with established glass bonding processes. These characteristics provide significant benefits for MEMS devices destined for aggressive industrial
Figure 1:
SCHOTT HermeS glass substrate wafers with hermetically-sealed Through Glass Vias (TGV)
the MEMS device, requiring wire bonding and the associated wafer real estate. Using HermeS glass wafers the ASIC can instead be integrated vertically above the MEMS chip, eliminating the need for wire bonds and creating a simplified structure in a smaller package (Fig. 2). According to Yutaka Onezawa, Sales
Manager for HermeS at SCHOTT Electronic Packaging, “this means that the footprint can be reduced by up to 80% compared to a conventional ceramic package. Various packaging configurations can be envisaged for pressure and gyroscope sensors, RF MEMS devices, and others.” “We are also able to apply state-of-the-art
Figure 1:
Schematic of a miniaturised, chip-sized and fully hermetic MEMS device
wafer-scale bonding, for example, anodic bonding with silicon, glass-frit and solder. Add in situ electrical connect testing and the customer is presented with an entirely wafer-level-capable packaging approach. The complete solution provides significant cost-of-ownership advantages in terms of yield and process reduction”, adds Onezawa. HermeS is currently available in three types
of glass (two of which are low alkaline) with two standard types of via material (tungsten and iron-nickel). Via size and pitch are variable and flexible, ranging from via diameters of 100µm down to 50µm and a pitch from 250µm down to 150µm, depending on the material combination and customer requirements.
SCHOTT
www.schott.com +49 6131 66 4140
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