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50 nanotimes News in Brief


Semiconductors // New Technique to Improve Efficiency of Semiconducting Materials, © Based on Material by Jared Sagoff, ANL, USA



A relentless move toward smaller and more precisely defined semiconductors has prompted researchers at the US Department of Energy’s (DOE) Argonne National Laboratory to develop a new technique that can dramatically improve the efficiency and reduce the cost of preparing different classes of semiconducting materials. The new discovery meets certain requirements of the international semiconductor “roadmap” all the way out to 2022-leapfrogging an anticipated ten years of progress with a single set of experiments. The drive to create smaller and smaller semiconductor components is often limited by a phenomenon known as domain collapse, said Argonne nanoscientist Seth Darling. Conventional lithography – the technique used to make patterns in materials – attempts to create features that are separated like the teeth of a comb. However, gaps in the resist that are too deep tend to collapse inwards, which makes the material useless. In 2010, Darling and his colleagues developed a technique known as sequential infiltration synthesis (SIS), which used gases to grow hard inorganic materials inside a soft polymer film. The work was supported by the DOE Office of Science through Argonne’s Center for Nanoscale Materials and the Argonne-Northwestern Solar Energy Research Center. One of the most notable benefits of SIS is that it eliminates the need for hard masks in photolithography, according to Darling. "Hard masks are a real pain when it comes to semiconductor processing – they’re expensive, complicated, reduce pattern quality and add extra steps," he said.


According to Darling, sequential infiltration synthesis has already been identified by leading semiconductor companies as a technology with the potential to overcome several different limitations. In a recent experiment, Darling and his Argonne colleagues showed that SIS can actually eliminate pattern collapse, enabling the fabrication of materials that have patterns with higher "aspect ratios," which measures the height of a feature divided by its width.


Generally speaking, lithography seeks to create patterns with higher aspect ratios while using as little resist as possible. "Usually, you need a certain thickness of the resist in order for the process to work," Darling said. "This new process enables us to do away with a lot of that problem." 


"One of the biggest advantages of this new study is that we’ve shown the possibility of using SIS for photolithography, which is one of the most industrially important processes," Darling said. "As there’s more and more demand for better electronics, the sizes of these semiconductors need to keep getting smaller and smaller, and it becomes that much more important for us to meet and exceed the benchmarks that we’ve set for ourselves."


Yu-Chih Tseng, Anil U. Mane, Jeffrey W. Elam, Seth B. Darling: Enhanced Lithographic Imaging Layer Meets Semiconductor Manufacturing Specification a Decade Early, In: Advanced Materials, Volume 24, Issue 19, May 15, 2012, Pages 2608-2613, DOI:10.1002/adma.201104871:


http://dx.doi.org/10.1002/adma.201104871


 




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