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techniques have seen intensive research and development continue as semiconductor companies and equipment manufacturers actively seek to tape out the next generation of devices. The scaling of semiconductor devices continues to move to smaller nodes at pace. At its May 2011 Investor Meeting, for example, Intel stated that it expects the 14nm node to be introduced to high volume manufacturing (HVM) in 2014. This type of aggressive timeline brings with it a new set of challenges throughout the supply chain, as the overriding goal is to ensure optimised device performance in ever smaller operating environments. Challenges such as the increasingly dense packaging solutions required for the multichip modules found at the heart of today’s multi- tasking smart devices are essentially making the design rules for these devices or components much more demanding. In addition, the physical limitations of devices and/or the manufacturing method, for example, migrating from CVD to ALD, are also driving the adoption and rate of material changes as integrations become more complex. It is therefore critical that the new materials and processes introduced are significant differentiators that not only improve functionality, but do so as an acceptable cost- benefit proposition. We are now seeing a growing emphasis on key strategic partnerships, with semiconductor manufacturers and tool manufacturers seeking to leverage the specific expertise of materials suppliers as the demand for custom materials solutions, using increasingly specialised materials, grows. From both a design and a manufacturing standpoint, and allied to a continued focus on cost of ownership (COO), deeper collaborations throughout the supply chain reflect the growing importance placed on highly functional device performance and process improvements. R&D, molecular design and test, the transport and delivery to the wafer of often volatile substances, and eventually scale up to HVM, the pooling of expert knowledge is essential if we are to continue to meet the challenges of manufacturing devices that are being custom tailored for integration with specific applications. Figure 1 shows the typical precursor design process undertaken by SAFC Hitech, which increasingly takes place within a deeply collaborative environment.


One of the main challenges facing materials


providers is putting in place the most appropriate solution for migrating to new materials and in doing so achieve device performance, control cost of ownership and offer an acceptable price point. Currently, we are looking at around two thirds of the periodic table, if not more, for developing the advanced molecules used in silicon semiconductor manufacturing processes. We are also looking at new molecules, innovative ways to produce them, new ways to test them, and to develop an understanding of their properties and their behavior on the surfaces where they are laid. This is one of the stages where the expertise of the materials supplier can really pay dividends and contribute to a lower COO.


For example, where we are depositing ZrO2 film we have the option of using either a liquid


or solid precursor. As it is significantly more cost- effective to purify a liquid to achieve the desired purity and quantity than it is to use a solid,


engineers developing a ZrO2 process can leverage the lower simply by using liquid in the vaporisation process. For process engineers, the development of the Zr oxide process using both precursors will essentially be the same. The customer presents the materials supplier with its need, to deposit Zr oxide. The supplier then has


15 Figure 1:


SAFC Hitech’s Typical Precursor Development Cycle


www.euroasiasemiconductor.com  Issue IV 2011


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