technology conference report
rhombus4
Panasonic has conduction and relatively low surface-charge scattering.
developed a
GaN monolithic Device testing of the germanium and InGaAs MOSFETs
inverter IC that revealed drain currents of 600 mA/mm and 200 mA/mm,
features six respectively, at a 2.5V gate bias swing, and maximum
normally-off transconductances of 340 mS/mm and 95 mS/mm,
gate injection respectively. On-off ratios for these devices are below
transistors. 10
4
, partly due to the high off-state leakage current that is
Credit: believed to stem from the surface leakage paths outside
Panasonic the active area. However, the authors say that this can be
addressed through proper device optimization and
improvements to the fabrication process.
A US team led by SEMTECH detailed its optimization of
a ZrO
2
dielectric at IEDM. This oxide is a promising
candidate for making a III-V MOSFET, because it has a
very high dielectric constant that is four times that of
Al
2
O
3
. However, the pairing of ZrO
2
with InGaAs leads to
voltages up to 360 V. The engineers believe that the border traps, interface traps, and interface fixed charges.
efficiency drop at higher voltages is caused by an The US researchers have partially addressed all these
increase in dynamic resistance and a rise in junction issues by inserting very thin (L
a
)AlO
X
layer between these
temperature, which could be reduced by improving the two materials. Adding this interlayer, which is only about a
heat sink in the GaN package. nanometer thick, cuts border traps and fixed charges by a
factor of three, and improves MOSFET performance.
Post-CMOS technologies Drain current increases by 50 percent, and maximum
The handful of papers presented on III-V transistors for transconductances by 75 percent.
logic applications included contributions from
SEMATECH, IMEC and Intel. For the last few years IMEC Intel’s wells
has been working on the development of a germanium Over the last few years Intel has been working on an
channel for p-type conductivity, and an InGaAs channel for alternative to the III-V MOSFET - the quantum well field
n-type conductivity – both types of conductivity are effect transistor (QWFET). This type of device can be
needed to make a suitable successor to CMOS. And at deposited on a silicon substrate, and it delivers an
IEDM the Belgium research institute unveiled their latest excellent drive current performance at low voltage, but
progress, the development of a common gate stack first-generation devices have suffered from a high leakage
process involving a sulfur-based treatment and deposition current at the Schottky gate.
of Al
2
O
3
. One of the merits of this approach is that it
avoids the need for either interfacial passivation layers or However, the researchers have now addressed this, and
native oxides, such as GeO
2
, between the channel and at the 2009 meeting they described the characteristics of
dielectric. a QWFET with a gate stack comprising 4 nm of TaSiOX
and 2 nm of InP. The new gate slashed leakage current by
Fabrication of the MOSFETs begins by taking germanium over three orders of magnitude, and led to the fabrication
and In
0.53
Ga
0.47
As substrates, cleaning then, removing their of 75 nm gate length transistors with a maximum
oxides and treating them in ammonium sulfide solution. transconductance of 1750 µS/µm, and a drive current of
Atomic layer deposition of 8 nm and 10 nm of Al
2
O
3
on 0.49 mA/µm at a drain-source voltage of 0.5 V.
germanium and InGaAs substrates follows at 300
degrees C, before these wafers are annealed at 400 Although the gate in this device is just 75 nm wide, the
degrees C. other structures are relatively large, and one of the next
goals for Intel is to reduce these dimensions while still
The researchers have studied the interface trap density in retaining the ability to move charges in and out of the
both structures. They found a relatively high density quantum wells. The researchers from SEMATECH and
( >1 x 10
13
/eVcm
2
) of acceptor-like traps near the IMEC face similar challenges, and the developers of
conduction band of germanium, but the density was nitride electronics at Panasonic, NEC and HRL still have
several hundred times less beside the valence band. With some way to go before their devices can be
InGaAs the opposite was observed: a relatively high commercialized. But all these compound semiconductor
density of donor-like traps on the valence band side, and devices are making progress, and it is a sure bet that
far fewer defects near the conduction band. These results even better results will be presented at the next IEDM,
suggest that it is possible to form a p-channel with a high which will be held in San Francisco, CA, from 6-8
density of free holes, and an n-channel with good electron December 2010.
40
www.compoundsemiconductor.net January/February 2010
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