conference report technology
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NEC adds neutralization
Like Panasonic, NEC has been developing a new
transistor technology. At IEDM it unveiled a GaN power
transistor featuring a novel piezo neutralization technology.
This addition to the device aids the control and
suppression of electrical currents when the power is
turned-off, and leads to low-power losses, high-speed
switching and high-temperature operation.
The authors of the paper say that conventional HEMTs
suffer from a large variation in threshold voltage. This is
caused by thickness variations in the AlGaN layer under
the gate that is etched down from 20-30 nm to just a few
nm to realize normally-off characteristics.
NEC sidesteps this issue with a five-layer design. This is
based on a metal-insulator-semiconductor (MIS) FET with
a piezo neutralization layer (see figure 1). The MESFET
produces normally-off operation, thanks to the switch from
a conventional buffer to one made from AlGaN.
Fig. 1 NEC unveiled a normally-off GaN MISFET that features a piezo
The NEC transistor benefits from the inclusion of a piezo neutralization layer. Setting the composition of this layer equal to that of
neutralization layer with an identical composition to the the buffer ensures a high threshold voltage uniformity thanks to complete
buffer. This causes the polarization charges formed cancellation of interface charges formed between these layers.
between these layers to cancel out, thereby equipping the Credit: NEC
FET with high threshold voltage uniformity. Realizing
similar levels of uniformity in conventional HEMTs is very
tough, due to variations in the thickness of an etched layer Ohm-mm. The three-terminal off-state breakdown voltage
– in an Al
0.15
Ga
0.85
N HEMT, just a one nanometer was more than 1000 V.
difference in thickness produces a 113 mV variation in
threshold voltage. NEC’s novel transistor also produces a The delegates at IEDM also heard about HRL’s
low on-resistance, thanks to the inclusion of an development of GaN HEMTs that were fabricated with a
Al
0.25
Ga
0.75
N layer. This second electron supply layer has a fluorine-based process. They have a breakdown voltage in
higher aluminum content than the first one, leading to two- excess of 1100V, and produce a leakage current of less
dimensional electron gases in both the channel layer and than 10 µA/mm at voltages below 550V.
the piezo neutralization layer. This creates a high sheet
carrier concentration of 6 x 10
12
cm
-2
that gives the The engineering team at HRL took two of the die and
MISFET its low on-resistance. formed a boost converter, a device for increasing DC
output voltage. This operated at a 200 kHz switching
The five-layer structure was grown by MOCVD on 3-inch frequency and delivered efficiencies of more than 96
silicon substrates. Nitrogen ion implantation isolated these percent for voltages up to 200V, and over 96 percent for
devices, and surface passivation was realized by
deposition of a SiN film. After a gate footprint was opened
in the SiN film, a BCl
3
plasma etch created the gate
recess. An Al
2
O
3
film provided the dielectric for the MIS
gate structure, and a Ni-Au film was employed for the Intel has
gate electrode in both gate structures. The NEC improved its
engineers fabricated Schottky gates across an entire 3- quantum well
inch wafer, and measured a standard deviation of the FET through
threshold voltage of 18 mV using a drain current of 1 the introduction
mA/mm and a drain voltage of 10V. They say that this of a gate stack
variation in threshold voltage is ten times smaller than that based on
for a conventional Al
0.15
Ga
0.85
N/GaN HEMT. TaSiOx and
InP. IQE carried
Transistors were fabricated with a source-to-gate out the growth
separation and a gate length of 1µm, and a gate-to-drain of the III-V
distance of 15 µm. At a threshold voltage of +1.5V the structure by
MISFET produced normally-off characteristics, a maximum MBE.
drain current of 240 mA/mm and an on-resistance of 20 Credit: Intel
January/February 2010
www.compoundsemiconductor.net 39
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