Feature: Communications design
controls on the multi-core processor. Te presence of both an FPGA and an MPU on the same chip,
however, means that the system design team has to straddle two worlds – FPGA and microprocessor – and work in two independent design environments. Te PolarFire SoCs’ toolchains feed into a configurator which generates: • Te ‘soſtware’ configuration – the C data structures for initialising the memory map – which will be used in the SoſtConsole integrated development environment (IDE);
• Te ‘hardware’ configuration – a so-called component – used in the Libero FPGA IDE. Te interaction between the two IDEs is shown in Figure 4. Design simulation is also supported by separate tools: Renode
(an open source soſtware development framework) for the soſtware running on the multi-core processor part, and ModelSim for the FPGA part of the SoC. Microchip has also made good provision for debugging the
complex applications that will run on the PolarFire SoC. Its on-chip-debugging mechanism communicates through a JTAG interface to debug tools: • C code can be debugged using a traditional openOCD debugger;
• Te FPGA debug tool is more specialised, with a debug mechanism embedded by default in the component to give dynamic access to any internal node of the FPGA matrix.
A dedicated tool, Smartdebug, uses this internal debugging circuitry to provide an intuitive means to debug the FPGA-based part of the application. Interestingly, the conditions for porting an application to the RISC-V
environment are similar to those within the Arm environment. No two Arm core-based devices will have the same memory map and, equally, no two RISC-V-based systems will share the same memory map. So porting from one Arm core to another in principle requires the same effort as porting from an Arm core to a RISC-V core.
Design-friendly development environment Te PolarFire SoC, then, offers the advantage of integrating in a single chip both programmable hardware capabilities and a high-performance, multi-core platform for soſtware applications. Tis hybrid architecture does entail the use of two development environments in parallel, but Microchip has taken great care to provide the user with a comprehensive set of tools that are extremely well integrated, and provide the capability for design teams to work productively in: • Creating or migrating the system; • Simulating the design; • Programming both the hardware resources in the FPGA portion of the chip, and application soſtware running on the processor cluster; and
• Debugging the system.
LED LAMPS
CUSTOM BUILD
CONTRACT ASSEMBLY
PANEL MOUNT INDICATOR
CUSTOM SOLUTIONS
TOWER LAMPS
KITTING FACILITY
STOCK HOLDING
Contact CML customer service now to discuss your requirements or for Stockist information.
CML Innovative Technologies Ltd. 69/70 Eastern Way, Bury St Edmunds, Suff olk, IP32 7AB, United Kingdom Tel: +44 (0) 1284 714700 email:
uksales@cml-it.com
www.cml-it.com
www.electronicsworld.co.uk September 2021 23
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50
