Column: JESD204 standard
Figure 3: Two interleaved ADCs – Nyquist zone
frequency component to the mismatch. With the offset mismatch, no signal is
needed to see the inherent DC offset of the two ADCs; however, to observe the gain mismatch, the ADCs need a signal. Gain mismatch results in a spur in the output spectrum that is related to the input frequency and the sampling rate and will appear at fS
/2 ± fIN . To minimise this spur,
a similar strategy is used as with the offset mismatch – the gain of one of the ADCs is chosen as a reference, and the gain of the other is set to match its gain value as closely as possible. Te better these gain values are matched, the smaller the resulting spur.
samples acquired, this DC offset changes; see Figure 4. Te output switches between these offset values at a rate of fS
/2, which
results in a spur in the output spectrum located at fS
/2. Since the mismatch itself
does not have a frequency component and is only at DC, the frequency of the spur that appears in the output spectrum only depends on the sampling frequency and will always appear at the frequency of fS
/2.
Te magnitude of the spur is dependent upon the magnitude of the offset mismatch between the ADCs – the greater the mismatch, the larger the spur. To minimise this spur caused by
the offset mismatch, there’s no need to completely null the DC offset in each ADC, since this would filter out any DC content in the signal, and would not work for systems using zero IF (ZIF) architecture, where the signal content is real and complex and includes data at DC. A more appropriate technique is to match the offset of one of the ADCs to the other. Choose one of the offsets as a reference, and match the offset of the other as closely as possible. Te better the match, the lower the resulting spur at fS
/2.
Gain mistmatch Figure 5 shows gain mismatch between two interleaved converters. Here there’s a
There are certain challenges when
interleaving ADCs, mostly in the form of spurs
Timing mismatch Te timing mismatch between two ADCs has two components: group delay in the analogue section of the ADC, and clock skew; see Figure 6. Te analogue circuitry within the ADC has an associated group delay, with a different value between the two. In addition, the clock skew has an aperture uncertainty component in each ADC and has a component related to the accuracy of the clock phases input to each converter. Similar to the gain mismatch spur, the
timing mismatch spur is also a function of the input frequency and the sample rate, and appears at fS
/2 ± fIN . To minimise the spur, the group delay
Figure 4: Offset mismatch
Figure 5: Gain mismatch
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