Feature: Communications design
sets of attributes: FPGAs and processors running real-time applications in a Linux operating environment. We say “different sets of attributes” because an FPGA consists of a programmable hardware fabric that supports parallel processing, whereas a processor is a fixed Instruction Set Architecture (ISA) hardware platform that executes and supports serial processing of instruction threads. The 2019 introduction of the Microchip PolarFire SoC FPGA
(Figure 1) bolted together these two platforms into a single system-on-chip that provides the following: • Te resources expected of a mid-density FPGA, including up to 461k logic elements, up to 1,420 18x18 math blocks, up to 33Mbits of user SRAM, eight fully-configurable PLLs, a high- speed DDR4 interface capable of data rates to 1.6Gbit/s, and multi-protocol transceivers operating at data rates to 12.7Gbit/s, with two hard-wired PCIe Gen2 end-points/root ports. Fabricated on a mature, low-power SONOS 28nm process, the FPGA achieves very low power consumption; see Figure 2 for comparisons with other devices.
A hybrid
architecture promotes productive design
By Patrice Brossard, EMEA Vertical Segment Manager – FPGAs and ASICs, Future Electronics
T
he inexorable progress of integration in semiconductors has been blurring the boundaries between different types of components for many years. By loading up one type of component with IP from a different kind, a sensor can become a machine-learning inference engine,
a microcontroller can be made to behave like an applications processor, and non-volatile memory can provide a secure hardware root-of-trust – a capability that normally requires a dedicated secure element. In late 2019, this blurring took another step forward with the merging of two types of system with almost entirely different
20 September 2021
www.electronicsworld.co.uk
• A multi-core applications processor consisting of a quad-core 64-bit RISC-V core cluster (RV64GC application core: 64-bit RISC-V with 2x32kbyte L1 cache with error correction code (ECC) and virtual memory support, and a separate 64-bit RISC-V monitor core, a RV64IMAC: 64-bit RISC-V with 32-bit integer registers, multiplication/division, atomic and compressed-mode support. All five cores operate at speed to 625MHz. The processor’s I/Os cover two Gigabit Ethernet controllers, a USB 2.0 On-The-Go controller and two CAN interfaces. Te combination provides system designers with a low-power single chip, with high thermal efficiency and military-grade security of an FPGA, and the deterministic execution capabilities provided by a fast processor. Such a hybrid SoC platform offers unique capabilities and
advantages in applications including systems operating in harsh environments, Artificial Intelligence (AI) inferencing at the edge, security-conscious applications, aerospace and defence systems and communications infrastructure, among others.
The hybrid processor/FPGA architecture At the heart of the PolarFire SoC FPGA is a deterministic, coherent CPU cluster of 4+1 RISC-V cores. RISC-V is a free and open functional specification for a processor’s ISA, and is backed by a growing ecosystem of development professionals, specifications, soſtware and other resources. For the CPU cluster in the PolarFire SoC, Microchip has
developed its own hardware architecture in collaboration with SiFive. A unique feature of the Microchip implementation is the freedom to turn off CPU branch prediction and make the memory sub-system fully deterministic. Tis eliminates all variation in execution time whilst maintaining the high processor performance provided by four of the RISC-V cores and relying on the deterministic features of the PolarFire FPGA. Te fiſth core, a monitor core, is used to manage the boot process and system configuration. Unlike the application
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