Feature: Communications design
Figure 3: In the PolarFire SoC’s AMP architecture, real-time functions directly access a dedicated portion of the L2 cache memory
processing cores, it does not include virtual memory support. All the SoC’s memories feature ECC with single error detection, providing a very high level of data integrity – a mandatory requirement in safety-critical applications, such as in aerospace. PolarFire SoC FPGA’s low power consumption is clearly
advantageous in battery-powered systems – and in any system, since there’s no need for a heat-sink or fan, reducing system cost, size and weight, and improving reliability.
Memory partition for real-time Linux operation Alongside the mid-density FPGA portion of the PolarFire SoC, Microchip has also implemented an architecture that provides real-time deterministic multi-processing. To run operating- system soſtware on a multi-core system, an MPU manufacturer can choose beween two types of multi-processing architecture: • In Symmetric Multi-Processing (SMP) all cores share the main memory. Here the cores are homogeneous; i.e., the OS treats each one equally. Tis means more identical cores can be added for increased performance.
• In Asymmetric Multi-Processing (AMP) the OS treats cores differently; i.e., they don’t share the memory or peripherals. Tis allows the system designer to assign certain kinds of tasks to one core, whilst leaving others free to run the OS, for example. Certain features of a typical SMP architecture, such as branch
prediction and cache misses, make it impossible for the SoC to operate deterministically. Execution time is inconsistent and cannot be guaranteed because every core is exposed to periodic interrupts. By contrast, AMP implementation allows the user to carve out a
part of the cache memory and reserve it for a real-time application’s exclusive use. Te PolarFire SoC supports both SMP and AMP modes, giving that choice, and even allowing a change of modes during field updates. Once the AMP mode is configured in the PolarFire SoC, the real-time application can run on one of the application cores, a real- time core in which branch prediction has been turned off; see Figure 3. Tis hardware structure supports the fully deterministic operation
of real-time functions alongside the Linux OS. In addition, Interrupt Service Routing (ISR) execution times are deterministic – a claim which can't be made as confidently for an SMP architecture implemented on an equivalent quad-core microprocessor based on Arm Cortex-A technology.
Hybrid FPGA/MPU system design A hybrid FPGA/MPU SoC offers a unique ability to meet the requirements of certain applications with a single chip. An application that concurrently performs local inferencing based on a machine-learning model and controls in real time the operation of a safety-critical motor, for instance, can implement the AI functions in the PolarFire SoC’s FPGA and the safety-critical
Figure 4: The relationship between the Libero IDE for the FPGA and the SoftConsole IDE for the MPU
22 September 2021
www.electronicsworld.co.uk
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