Column: JESD204 standard
JESD204B and
interleaved ADCs
By Jonathan Harris, Applications Engineer, Analog Devices
I
nterleaving analogue-to-digital converters (ADCs) brings several advantages across many segments of the market today: In communications infrastructure, there is a constant push for higher-
sample-rate ADCs to allow for multiband, multicarrier radios, in addition to wider bandwidth requirements for linearisation techniques like digital pre-distortion. In military and aerospace, highersample rate ADCs enable multipurpose systems used for communications, electronic surveillance and radar, among others. In industrial instrumentation, higher sample rate ADCs help accurately measure higher- speed signals. Tere are several examples of Analog
Devices’s interleaved ADCs with the JESD204B interface, which include a12- bit/2.5GSPS three-way interleaved ADC (AD9625), and a ping-pong-interleaved ADC (AD9680).
Interleaving When ADCs are interleaved, two or more ADCs with a defined clocking relationship are used to simultaneously sample an input signal and produce a combined output that results in a sampling bandwidth at a multiple of the individual ADCs. An n number of ADCs increases the effective sample rate by a factor of m. So, if two ADCs with a sample rate of fS interleaved, the output is 2× fS
are . Teir clock
phase relationship is governed by Equation 1, where n is the specific ADC and m is the total number of ADCs:
(1)
As an example, two ADCs with a sample rate of 100MSPS are interleaved (Figure 1),
DC offset mismatch Since each ADC has an associated DC offset value, when interleaved and then
achieving a sample rate of 200MSPS, with a clock phase relationship per Equations 2 and 3:
(2) (3)
Notice in Figure 1 the 180° clock phase
relationship and the way the samples are interleaved. Te input waveform is alternatively sampled by the two ADCs, with the interleaving implemented by a 200MHz clock input that’s divided by two. Figures 2 and 3 show the same concept:
by interleaving the two 100MSPS ADCs, the sample rate increases to 200MSPS, which extends each Nyquist zone from 50MHz to 100MHz, doubling the available operational bandwidth. Tis means that radio systems can support a larger number of bands, radar systems can improve their spatial resolution, and measurement equipment can achieve greater analogue input bandwidth.
Interleaving challenges However, there are certain challenges when interleaving ADCs, mostly in the form of spurs that appear in the output spectrum, that result from the imperfections associated with the interleaving process. Tese imperfections are basically mismatches between the two interleaved ADCs, of which there are four basic types – offset, gain, timing and bandwidth mismatches.
Figure 1: Two interleaved 100MSPS ADCs 16 September 2021
www.electronicsworld.co.uk
Figure 2: Two interleaved 100MSPS ADCs – clocking and samples
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