Column: Silicon systems design


Figure 3: Hierarchical DFT sign-off across core, block and full-chip levels (Image: Siemens)


introduced open frameworks for chiplet interoperability and verification. The OCP universal D2D link layer provides a common language and methodology for interoperability testing across dies from different suppliers. Complementing this, the OCP system-in-package (SiP) test white paper defines open practices for test access, pre-assembly screening and system-level validation. These initiatives help the industry move from isolated, vendor-specific flows to standardised validation across a shared ecosystem.


AI-assisted DFT and test flow efficiency Chiplet integration increases the test’s dimensionality. Pattern optimisation, defect localisation and thermal-aware scheduling all become more demanding as die count rises. AI-supported techniques are now demonstrating clear improvements in maintaining coverage while reducing pattern volume. Machine learning models can predict


likely defect regions using historical failure data, reduce ATPG pattern sets without compromising fault coverage, and adapt scheduling to real-time power and thermal conditions. Figure 3 shows how hierarchical DFT


enables sign-off at the core, block and full-chip levels by replicating a validated reference core and distributing packetised scan data across the wider design. For multi-die designs, these


capabilities are particularly valuable. High-speed interconnect patterns require specialised validation, memory fabrics require voltage-dependent pattern generation and workload-dependent behaviour must be captured for accurate defect prediction. AI-supported diagnostic analysis also accelerates post-silicon bring- up by rapidly correlating observed signals with expected device behaviour. T is shortens the path from fi rst power-on to functional validation, enabling faster yield recovery.


Post-silicon bring-up Chiplet complexity becomes most visible in the bring-up phase. Inter-die timing variations, thermal gradients and power distribution imbalances often emerge only once the whole system is active. Reliable debug depends on test structures that expose die boundaries, interconnect layers and internal scan access with sufficient resolution.


IEEE 1838 provides the structural


ingress required for controlled access to stacked dies. AI-supported analysis accelerates rootcause identification by correlating anomalous behaviour with expected device models. OCP frameworks ensure that these processes remain interoperable across heterogeneous suppliers. As a result, test, debug and bring-up operate as a unified flow rather than as separate engineering domains.


18 December 2025/January 2026 www.electronicsworld.co.uk


Strengthening testability in the chiplet era The emerging chiplet ecosystem depends on openness. Multi-vendor testability is achievable only when companies align on standards, data formats and validation methods. The Open Compute Project illustrates this effectively. Its D2D link layer and system-in-package test frameworks show how organisations can coordinate test practices without compromising competitive differentiation. If AI-enabled DFT continues


to develop within this same open environment, intelligent automation will become accessible to design teams of all sizes. Openness expands capability, accelerates adoption and ensures that the benefits of chiplet- based design extend across the wider industry. In effect, a robust strategy for chiplet


testability requires four foundations: • IEEE 1838-based die wrappers; • UCIe-compliant interconnect with reliable metadata exchange;


• AI-integrated ATPG, optimisation and diagnostics;


• OCP-supported interoperability frameworks. Chiplets offer a scaleable path for


semiconductor innovation over the next decade.


This column continues in next month’s edition of Electronics World


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