Column: Silicon systems design


The steps to silicon sign-off


a distributed multi-die system. These limitations reduce bring-up efficiency and raise the likelihood of latent defects escaping into production. Bring-up is the process of transforming individual chiplet designs from a concept into a fully functional, integrated physical system, or silicon.


Standards enabling multi-vendor chiplet testability


IEEE 1838 IEEE 1838 introduces a standardised test access architecture for 3D ICs and chiplet stacks. Figure 2 shows how IEEE 1838 structures per-die wrapper registers (DWR), serial control modules (SCM) and the flexible parallel port (FPP) for scaleable test data access in a 3D multi-die stack. T e standard defi nes wrapper registers


at the die level, a standard TAP-based access mechanism and a fl exible parallel port for scaleable data movement. T ese elements ensure that any IEEE 1838-compliant die provides a predictable test interface, whether used individually or within a larger multi-die system.


UCIe UCIe extends this by defining a common die-to-die interconnect, including guidance for test structures, lane monitoring and metadata exchange. UCIe also supports a ‘Known Good Die’ methodology, which is essential for reducing system-level test burden.


Together, IEEE 1838 enables vertical


stack access and UCIe enables horizontal multi-vendor interoperability. These two foundations form the structural basis of modern chiplet test architecture.


OCP D2D and SiP testing The Open Compute Project (OCP) has


Figure 2: IEEE 1838 test access architecture (Image: Imec)


www.electronicsworld.co.uk December 2025/January 2026 17


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