Column: Silicon systems design
The new design- for-testability landscape for chiplets
By Mike Bartley, CEO, Alpinum C
hiplet-based architectures are shaping the next generation of semiconductor design: Instead of fabricating a single monolithic device,
designers increasingly assemble multiple specialised dies into a single package. This improves yield, modularity and scaleability, but it also increases the complexity of the test. Traditional Design for Testability
(DFT) methodologies were created for monolithic ICs and did not account for multi-die integration, heterogeneous IP sourcing or high-density die-to-die
communication. For chiplets to scale, DFT must be defined at the architectural level rather than introduced late in the design cycle.
Chiplets disrupt traditional DFT In a monolithic device, controllability and observability are predictable and local. Scan insertion, automatic test pattern generation (ATPG), built-in self-test (BIST) and boundary scan give structured access to internal logic even after packaging. These assumptions no longer hold
in a multi-die chiplet system. Logic is distributed across dies that don’t share
Figure 1: A 2.5D chiplet assembly showing chiplets on a silicon interposer with microbumps and TSVs (Image: Jinwoo Kim and co-authors)
the same routing topology, physical interfaces or process technology. Interconnect may pass through interposers, microbumps or through- silicon via (TSV) based vertical links, each of which introducing points where visibility can be lost. Figure 1 shows how chiplets are mounted on a silicon interposer using microbumps, TSVs and C4 bumps, highlighting the physical interfaces where test visibility can degrade in multi-die systems. Chiplets disrupt classical DFT in
three fundamental ways: First, internal visibility becomes inconsistent because individual dies may not expose uniform test interfaces or wrapper structures. Second, defects may occur between dies rather than inside them, making interconnect validation as critical as die-level testing. Third, conventional scan chains were never designed to cross package boundaries or validate high- speed die-to-die fabrics. As packaging density increases, the
limitations of classical DFT become more pronounced. Multi-die assemblies, therefore, require architectural test support beyond traditional boundary scan and must adopt standardised access mechanisms defined for stacked and modular devices. In essence, classical DFT remains
essential, but its effectiveness declines as architectural complexity increases. Greater logic depth increases pattern count, test time and automated test equipment (ATE) costs. JTAG Boundary Scan Standard IEEE 1149.x is valuable for pin access but insufficient for buried interconnect structures inside chiplet assemblies. Mixed-node integration and heterogeneous IP reuse can further create inconsistencies in test structures, unless alignment is enforced at the architectural stage. Access points often fail to penetrate
stacked regions, and controllability mechanisms that work well within a single die do not naturally extend across
16 December 2025/January 2026
www.electronicsworld.co.uk
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