EMC & Circuit Protection
of the switch is clamped by the internal protection diodes before the overvoltage protection of the switch is activated and the switch opens to fully isolate the fault from the downstream circuitry. Figure 3 shows the regions of operation for a system input that interfaces with the outside world. The leftmost region (in green) represents normal operation, where the input voltage is between the supply voltage ranges. The second region from the left (in blue) represents the range of possible persistent DC or long duration AC overvoltages presented to the input due to loss of power, miswiring, or short circuits. Also included in the diagram, on the far right hand side (in purple), is the trigger voltage for the internal ESD protection diodes of the overvoltage switch. The TVS breakdown voltage (in orange) must be selected to be less than the maximum standoff voltage of the overvoltage
protection switch and also greater than any know possible persistent DC or long duration ac overvoltage, in order to avoid inadvertently triggering the TVS. The protection circuit in Figure 4 can withstand up to 8 kV IEC ESD (contact discharge), 16 kV IEC ESD (air discharge), 4 kV EFT, and 4 kV surge. The ADG5412F (±55 V overvoltage protection and detection, quad SPST switch from Analog Devices) can withstand the overvoltages caused by ESD, EFT, and surge transients, while the overvoltage protection combined with the protection diodes on the drain protects and isolates downstream circuitry. The protection network consists of a TVS and an optional low value resistor. The resistor is required to achieve the higher levels of ESD and EFT protection, as it prevents the internal ESD protection cell of the overvoltage switch from triggering before the TVS clamps the voltage on the
Figure 5: Operation of OVP during a surge event
input. Figure 4 also shows the various current paths during a high voltage transient event. The majority of the current is shunted to ground through the TVS device (Path I1). Path I2 shows the current that is dissipated through the internal ESD diodes on the output of the ADG5412F, while the output voltage is clamped to 0.7 V above the supply voltage. Finally, the current in Path I3 is the residual current level that the downstream components must withstand.
Figure 4: Protection circuit
Surge protection This measurement in Figure 5 shows the result of a 4 kV surge transient applied to the input of the protection circuit. The
voltage at the source can increase beyond the breakdown voltage of the TVS up to its maximum clamping voltage. The overvoltage protection switch in this circuit has a reaction time of approximately 500 ns and the voltage on the drain of the device is clamped at 0.7 V above the supply during this first 500 ns time period. The peak current flowing to the downstream device is just 608 mA during this time period and after approximately 500 ns, the switch is seen to turn off and isolate the downstream circuitry from the fault. Again, this is less than the energy transmitted during a 1 kV HBM ESD event.
www.analog.com
www.cieonline.co.uk
Components in Electronics
September 2018 41
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52
