Security & Monitoring
Add authentication security to automotive end points using a single pin By C. Michael Haight, Analog Devices
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ncreasing electronic content on vehicles presents expanded attack surfaces to hackers. Digital authentication can reduce the risk of theft and counterfeiting of genuine and approved high-quality
components. In mission-critical automotive applications such as ADAS and EV Batteries, low-quality counterfeits can introduce safety risks if their performance is degraded compared with genuine components. Stolen components may not be calibrated to operate properly in a different vehicle. By adding a single authentication IC, you can now authenticate a component with only one signal between an ECU and end point component, as shown in Figure 1. Traditional approaches to component security and authentication use a secure microcontroller or even automotive Hardware Security Module (HSM). While a robust solution, this is costly and involves many electrical contacts from the host controller, significant PC board area, and extensive software development and verification to prevent bugs. Now, by adding just one compact, fixed-
Figure 1. ECU and End Point Block Diagram
function IC, the end point can be secured by running only one signal plus ground reference in a shielded cable between ECU and end point. The DS28E40 from Analog Devices implements the 1-Wire protocol, which uses half-duplex communication and harvests power for the device parasitically through the communication line, thus reducing the need for
a dedicated power line in the cable. Harvested energy is stored in an external capacitor. Most automotive ECUs include a high-performance microcontroller, and only one open drain PIO pin with a pullup resistor is required for bidirectional communication. Security algorithm computations require up to 16mA, beyond the pullup’s sourcing ability. If PIO1 can switch
between open drain and push/pull configuration with sufficient current sourcing, then drive logic 1 during computations. Alternately, a low-impedance bypass FET can be added and controlled by PIO2 to deliver sufficient current. The device employs the ECDSA public key security algorithm, with library and code examples available to easily implement the security layer on the ECU host processor. With this asymmetric security algorithm, key management is simplified by allowing the host to directly read the unique public key from the DS28E40. Then the host can issue random challenge messages to the DS28E40, which digitally signs the challenge with its internal private key that is never exposed to the outside world. If the host verifies the signature matches the public key, then the automotive end point can be trusted by the ECU. The DS28E40 is qualified to AEC Q100 grade 1 (-40°C to +125°C) and is available in a 3mm x 3mm side-wettable flank TDFN package.
www.analog.com
RISC-V Physical Memory Protection (PMP) architectural validation test suite for high quality security applications
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mperas Software, a leader in RISC-V simulation solutions, has announced the beta release of the ImperasDV architectural validation test suites for RISC-V Physical Memory Protection (PMP). The open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an optimized processor while leveraging the ecosystem of compatibility. The RISC-V Privileged Specification includes PMP as a fundamental approach to memory protection that is essential in security applications that depend on TEE (Trusted Execution Environments) such as Keystone, OpenTitan, and many other leading techniques for security protection. Thus, functional verification of PMP is essential for any RISC-V processor targeted at security applications.
RISC-V processor implementations for
www.cieonline.co.uk
security applications use physical memory protection (PMP) as a way to ensure memory isolation between key security applications and other activities. The RISC-V PMP specification provides a flexible and comprehensive approach based on control registers for the parameterization of modes to control the memory access, permissions, and policy. By using control registers, the actual policy and operation can be configured in software using the available hardware resources. The PMP policy thus can be configured to control the initial processor boot process and is fundamental to many systems that rely on a TEE for security applications.
RISC-V processor functional verification needs to ensure the design behaves as expected. In the case of the PMP functionality, due to the wide range of possible configurations and implementations, the architectural validation test suite also needs
to cover the vulnerabilities that arise from a design error that enable an unnecessary or unwanted option. While some processor developers undertake both the design and test phases of a project, the advantage that 3rd party tests provide is an independent interpretation of the specification and thus offer a valuable additional safeguard. This is especially important when specification options selected for the target device are used to direct the test plan, since an unintended design error that includes an unnecessary and therefore untested feature could allow for a security vulnerability.
The Imperas Physical Memory Protection (PMP) architectural validation test suites are available now to ImperasDV users as a beta release, with a full production release scheduled for Q2 2022.
Imperas.com/ImperasDV. Components in Electronics March 2022 39
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