Embedded Technology
Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
By Jason Zhu, CEO, GOWIN Semiconductor W
hen a designer of telecoms equipment such as a server or switch specifies a field-programmable
gate array (FPGA) for a high-speed data interfacing function, performance is the most important criterion for choosing the preferred device. If the rule of thumb in specifying an electronics component is that the designer can have one or two of high speed, low power consumption, small size and low cost, but not three or all four of these attributes, the telecoms equipment manufacturer will prioritize high speed above the other factors. This has given the manufacturers of high- end, high-density FPGAs a strong incentive to develop products which are packed with high-performance SerDes capabilities, and which support the high-speed communications protocols – PCIe, Ethernet, Infiniband and so on – on which communications service providers’ fibre networks are based. These FPGAs might be large, they might be expensive, and they might be power-hungry – but this is of little importance to equipment manufacturers serving the telecoms market, as long as they are fast.
How different it is in other parts of the embedded systems market: in portable and wearable consumer devices, in particular, the cost, power consumption and size of an FPGA are impossible to overlook. This has meant that the FPGA’s role in consumer devices has generally been limited to functions which basic FPGAs – small, low-power, low-density and low-cost products – can perform, such as: Glue logic integration Simple counter Basic state machine Control logic I/O and interface bridging I/O expansion Aggregation of multiple sensor inputs Voltage monitoring
36 March 2025
Fig. 1: To create immersive experiences, a VR headset requires ultra high-definition display capability, and the internal data bandwidth to support it
For anything more demanding, the FPGA market did not in the past provide products which could meet the consumer market’s speed/cost/size requirements. In fact, there was no demand for the FPGA’s high-speed data interfacing capabilities for as long as embedded devices were handling relatively small amounts of data to support undemanding input and output devices such as a basic camera or a small display. But the consumer world is changing: technology and consumer demand are driving data throughput off the scale. We are discovering that there is almost no limit to people’s appetite for vivid, ultra high- definition (UHD) video and AI-enhanced high-resolution imaging, even in space- and power-deprived wearable products such as AR/VR headsets and smart glasses (see Figure 1). For instance, a VR headset will typically
Components in Electronics
be required to cram the type of UHD content more normally viewed on a large TV screen on to two synchronized displays. Not only must the output achieve 4K or even 8K resolution, it must also be rendered at a higher frame rate – typically 120 frames/s – than a standard TV achieves, to avoid the risk of motion blur. This demand for higher video bandwidth is leading manufacturers of embedded systems aimed at the consumer market to migrate from interfaces such as MIPI D-PHY for video to higher-speed alternatives such as MIPI C-PHY or DisplayPort. And this in turn calls for the type of high-speed SerDes capability that the telecoms equipment designer uses an FPGA to provide. But we know that the high-speed FPGAs developed for the telecoms market are not suitable for consumer devices. This is why I foresee the emergence of a new category of FPGA at
the low-density, low-cost end of the market that has previously been limited to basic logic functions.
This new-generation FPGA for more advanced embedded systems such as VR headsets and smart glasses will be optimized for high-speed SerDes functions: it will offer not only raw high-speed SerDes capability, but will also specifically support the protocols that the new consumer devices are using, such as MIPI C-PHY and PCIe, either as soft-coded IP or even hard-coded into the silicon (see Figure 2). This SerDes capability will be backed by more generous provision of high-speed memory than is usual in low-end FPGAs.
Optimized for data-interfacing and data- bridging functions, this new generation of FPGA will provide limited scope for implementing other logic functions, with
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