Supplement: Power
Active biasing solution for pHEMT power amplifiers
By Gweneivere Lasay, product applications engineer, Analog Devices P
seudomorphic high electron mobility transistors (pHEMT) are depletion devices that have drain-source channels with resistances close to 0Ω. This property allows the devices to operate at high gain at high switching frequencies. However, the high conductivity of the drain channel might result in a burnout on the devices if a proper gate and drain bias sequencing is not applied. In this article, we will explore the operation of depletion mode pHEMT radio frequency (RF) amplifiers and how they can be practically biased. Depletion mode field-effect transistors (FETs) require a negative gate voltage and turn on/off must be carefully sequenced. Fixed gate voltage and fixed drain current circuits will be presented and compared. We will also take a close look at how the noise and spurs of these biasing circuits affect RF performance.
Introduction
Figure 1 shows a simplified block diagram of a depletion mode pHEMPT RF amplifier. The RF signal path through the device is from gate to drain with AC-coupling capacitors to decouple the RF signal from the DC bias voltages on the drain and gate. The main supply voltage is applied to the drain of the FET transistor through an inductor.
One important property of depletion mode devices is that the drain-to-source resistance is close to 0Ω when the gate voltage is equal to 0V. As a result, to operate the device, a negative voltage must be applied to the gate. In Figure 1, this voltage is applied through an on-chip inductor.
One drawback of this biasing method is that the two supplies cannot be turned on at the same time. Applying a drain bias voltage
before the gate bias voltage causes a sudden increase in drain current that will quickly cause burnout. Because of this, a negative gate bias voltage must first be applied to pinch off the channel. When turning the amplifier on and off, the procedures in Table 1 should be used. In practice, the pinch-off step can be skipped. For example, if the final gate voltage for normal operation is known, that voltage can be immediately applied without going through the pinch-off step.
Fixed gate voltage biasing Figure 2 shows a power management circuit for a depletion mode RF amplifier
that establishes and maintains a fixed gate voltage. This uses a switching regulator, low dropout (LDO) regulator, and load switch to develop the drain voltage. The gate voltage is developed by the ADP5600, which contains a voltage inverter and an LDO regulator. The drain current is set by the feedback resistors of the negative voltage LDO regulator. To ensure safe power sequencing, the enable (EN) pin of the switching regulator is tied to the power good (PGOOD) signal of the negative voltage generator. This ensures that the negative gate voltage is always present before the drain voltage.
The main disadvantage of this circuit is that Figure 2. Fixed gate voltage biasing
Figure 1. A simplified architecture of a depletion mode RF amplifier Power-On Sequence
1. Apply the negative voltage to the gate placing the gate in pinch-off mode.
Power-Off Sequence 1. Remove the RF signal.
2. Apply the positive voltage to the drain. 2. Decrease the gate voltage (more negative) to pinch off the gate.
3. Increase the gate voltage to achieve the quiescent current.
4. Apply the RF signal. Table 1. Amplifier procedures 30 March 2025 Components in Electronics
www.cieonline.co.uk 3. Reduce the drain voltage to OV. 4. Increase the gate voltage to OV.
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