POWER
DC2626A are used4
. As shown in Figure 7a
MOSFETs placement and the DC2626A has a fair comparison, the two demo boards decoupling capacitors, and tested at 36V to
7c shows the tested VIN AC ripple during
Figure 4: Horizontal hot loop: (a) top view and (b) side view
MOSFETs placement, the VIN ripple has lower magnitude and higher resonant freq uency, hence validating the smaller PCB ESL due to a shorter hot loop path. On the contrary, because of the longer hot loop and higher ESL, the straight MOSFETs placement
Table 1: Extracted PCB ESRs and ESLs in Different Hot Loops by Using FastHenry
(b) to further reduce the loop ESR and ESL. In Case (d), a 5mm × 6mm MOSFET is replaced with two 3.3mm × 3.3mm MOSFETs in parallel. The loop length is further shortened thanks to the smaller MOSFETs footprint, leading to 7% reduction of the loop impedance. In Case (e), when a ground layer is placed under the hot loop layer, the hot loop ESR and ESL are further decreased by 2% compared to Case (d). The reason is that eddy current is generated on the ground layer, which equivalently reduces the loop impedance. In
Case (f), another hot loop layer is constructed as the bottom layer. If two paralleled MOSFETs are symmetrically placed on the top layer and bottom layer and connected through vias, the hot loop PCB ESR and ESL reduction are more obvious because of the paralleled impedance. Therefore, smaller sized devices placement on top and bottom layers lead to the lowest PCB ESR and ESL.
To experimentally verify the impact of the 4-switch synchronous buck-boost controller
results in much higher VIN ripple magnitude and slower resonant frequency. A higher input voltage ripple also causes a more severe EMI emission according to the EMI test results in the study of Cho and Szokusha4
.
Hot Loop PCB ESR and ESL vs. Via Placement
The vias placement in the hot loop also has a critical impact on the loop ESR and ESL. As layer PCB structure and straight power FETs placement is modelled. The FETs are placed on the top layer and the second layer is a ground plane. The parasitic impedance Z2
between CIN GND pad and M2 source pad is part of the hot loop and is studied as an Table 3 summarises and compares the
simulated ESR2 and ESL2 with different via placements.
In general, adding more vias reduces the
reduction of ESR2 and ESL2 is not linearly proportional to the number of vias. The vias close to the terminal pads give the most obvious reduction in PCB ESR and ESL. Therefore, for hot loop layout design, several critical vias must be placed close to the pads
of CIN impedance.
Figure 5: Demo board testing results: difference between horizontal loop and
(c) VIN ripple during M1 turn-on at 15A output
Table 2: Extracted Hot Loop PCB ESR and ESL with Various Device Shapes and Positions in FastHenry
32 JULY/AUGUST 2023 | ELECTRONICS FOR ENGINEERS
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