POWER


How to optimise switching power supply layout by minimising hot loop PCB ESRs and ESLs


Jingjing Sun, product applications senior engineer, Ling Jiang, product applications ,anager, and Henry Zhang, product applications senior director, all with Analog Devices, say minimising hot loop PCB ESRs 


F


or power converters, a hot loop PCB layout with minimum parasitic parameters  the voltage ringing, and reduce the electromagnetic interference (EMI). This article discusses the optimisation of hot loop layout design by minimising the PCB equivalent series resistances (ESRs) and equivalent series inductances (ESLs). This article also investigates and compares impact factors including decoupling capacitor positions, power FET sizes and positions, and via placements. Experiments are conducted to verify the analysis, and effective methods of minimising the PCB ESRs and ESLs are summarised.


Hot Loop and PCB Layout Parasitic Parameters


The hot loop of a switching-mode power


 frequency (HF) AC current loop formed by the HF capacitor and adjacent power FETs. It is the most critical part of the power stage PCB layout because it contains high dv/dt and di/dt noisy content. A poorly designed hot loop layout suffers from a high level of PCB parasitic parameters, including the ESL, ESR, and equivalent parallel capacitance (EPC),   and EMI performance.


Figure 1 shows a synchronous buck step- down DC-to-DC converter schematic. The hot loop is formed by MOSFETs M1 and M2 and


the decoupling capacitor CIN. The switching actions of M1 and M2 cause HF di/dt and dv/


dt noise. CIN provides a low impedance path to bypass the HF noisy content. However, parasitic impedance (ESRs, ESLs) exists within


30 JULY/AUGUST 2023 | ELECTRONICS FOR ENGINEERS


the components’ packages and along the hot loop PCB traces.


The high di/dt noise through ESLs causes HF ringing, furthermore, resulting in EMI. The energy stored in ESL is dissipated on ESRs, leading to extra power loss. Therefore, the hot loop PCB ESRs and ESLs should be minimised to reduce the HF ringing and improve 


An accurate extraction of the hot loop ESRs and ESLs helps predict the switching performance and improve the hot loop design. Both components’ package and PCB traces contribute to the total loop parasitic parameters. This work mainly focuses on the PCB layout design. There are tools for users to extract the PCB parasitic parameters, such as Ansys Q3D, FastHenry/FastCap, StarRC, etc. Commercial tools like Ansys Q3D provide accurate simulation but are usually


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