FEATURE ELECTRONIC DESIGN AUTOMATION
DESIGN SEPARATELY, INTEGRATE SEAMLESSLY
Tom Spohrer at Microchip explores how the latest dual-core digital signal controllers are speeding development for design engineering teams
T
he challenge to develop increasingly sophisticated designs while completing
them within shorter schedules is a key issue. The requirements for products that include additional functional safety features or complex communications capabilities adds to the design complexity and challenges. Sometimes compounding these challenges is the geographically- dispersed nature of the engineers available to work on a particular product. For example, a contemporary automotive DC to DC converter design project team might be comprised of power supply firmware developers from one site or country and communication stack firmware developers from another site or country. Integrating the code developed at multiple locations onto the same microcontroller can increase the schedule risk due to the complex interaction between the separately designed firmware.
THE DUAL-CORE DSC FAMILY A new family of dual-core Digital Signal Controllers (DSCs) in a single chip, enables easier software integration. Microchip Technology’s dsPIC33CH has one core designed to function as a master, while the other functions as a slave. In this master- slave architecture, the slave core can be used for executing dedicated, time-critical control code, while the master core is busy running system-level functions, including user interface (UI), monitoring and communications, customised for the end application. The dsPIC33CH is designed to facilitate
independent code development for each core by separate design teams – but later enables seamless integration when they
14 FEBRUARY 2019 | ELECTRONICS
are brought together in one chip. Its dual independent cores simplify firmware development, enabling a multi-team software development approach, with two workflows running in parallel. Time-critical control loops can be separated from housekeeping functions such as UI, monitoring and diagnostics, and communication. This speeds the development process, allows each core’s code to be individually and more effectively optimised, with minimal code interaction between the two cores, easing the debug process.
IDEAL APPLICATIONS The dsPIC33CH family is optimised for high-performance digital power, motor control and embedded applications requiring sophisticated algorithms. Typical power applications for this dual-core controller include wireless charging, server power supplies, DC to DC converters, chargers and inverters. The family will also be popular for motor control in pumps, fans, drones, robotics, power tools and consumer appliances. As a high- performance DSC, these devices excel when used in automotive electronic sensors, industrial automation and control and medical diagnostic equipment. Benefiting from two microcontroller cores on the same die, this family can provide the performance required for gateways and central processors for IoT applications. For example, in a digital power supply,
the slave core manages the math- intensive algorithms, closing the control loop in firmware by running latency- critical compensator algorithms, while the master core independently manages the
PMBus protocol stack and provides system monitoring functions, increasing overall system performance and responsiveness. In an automotive fan, pump or other
motor control application, the slave core can be dedicated to executing time-critical speed and torque control, while the master core runs functional safety routines and manages the Controller Area Network Flexible Data rate (CAN-FD) stack for robust communications, as well as other system-level functions, including monitoring and diagnostics. In other high-performance embedded
applications, such as electronic sensors used in automotive or IoT systems, the slave core accelerates math-intensive functions, such as DSP filtering of sensor inputs, while the master core facilitates reliability and fault-tolerance for safety- critical applications. The master core has 64 to 128 Kilobytes of program flash, with ECC and 16KB RAM, while the slave has 24KB of program RAM, with ECC and 4KB data RAM. Core frequency for the master is 90 MIPS at 180MHz, while the slave delivers 100 MIPS at 200MHz. Additionally, both processor sub-systems have their own interrupt controllers, clock generators, port logic, I/O MUXes and PPS. The device is effectively the equivalent of having two complete dsPIC DSCs on a single die. In a performance-critical calculation, the
new controller achieves core performance almost twice as fast as the previous generation – with latency of 280ns, compared to 543ns. Microchip’s dsPIC33CH is optimised for
high-performance and time-critical, real- world embedded control applications. This family enables separate code design and seamless integration, while also reducing system cost and size.
Microchip
www.microchip.com T: 0800 056 5113
/ ELECTRONICS
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