FEATURE INTEGRATED CIRCUITS
The demands on FPGAs in contemporary electronics are exceeding this generation’s grasp. Frank Ferro, senior director, product marketing, IP cores, Rambus, discusses how their range of compute accelerators could change the tide in the designer’s favour
H
igh-performance machine-learning and networking applications are
powering trends, such as the industrial IoT. Characterised by massive quantities of data, their need for speed challenges data centres and embedded systems to keep pace.
In response, high-performance compute accelerators are combined with CPUs and GPUs (Graphics Processing Units) to blend scalar and vector processing (single-instruction/multiple decode) for optimum handling of compute-intensive workloads. However, relentless demand to support
extra services, more customers and intensive workloads is now driving the emergence of high-performance accelerators based on a new class of FPGA. These devices are combining FPGA configurability with ASIC routing structures and compute engines, tightly coupled through efficient shared instruction and data memory, integrated alongside scalar cores and FPGA fabric, all interconnected on a high-bandwidth “network on chip”. The resulting engines deliver multi-
tera-operations per second (TOPS) compute performance, and can be tailored for workloads such as video transcoding and network acceleration. Leading cloud-services providers are adopting FPGA acceleration, not only to boost performance, but also to gain flexibility to adjust quickly to changes in fast-moving technologies. With this increase in compute-engine performance, attention must now shift to associated subsystems, such as memory and network interfaces, that could potentially restrict the flow of data in and out of the system. The data-throughput demands of self-driving vehicles provide
34 SEPTEMBER 2019 | ELECTRONICS
just one striking example. Today’s vehicles typically use DRAM memory with an interface bandwidth of less than 60Gb/s. Micron estimates that more than eight-times the memory bandwidth is needed to support level three and four autonomous-driving modes - as much as 512Gb/s to 1024Gb/s - tipping GDDR memory as the technology best positioned to meet the demand.
HIGH-BANDWIDTH GRAPHICS MEMORY GDDR (Graphics Double Data-Rate RAM) originally emerged for use with video cards, game consoles, and PC graphics. Larger bus widths, more channels, and faster data transmission result in a performance increase compared to ordinary DDR memory. The latest generation, GDDR6, introduces a two- channel, 16n prefetch architecture that raises throughput to 16Gb/s per pin, resulting in 64Gb/s total data- I/O bandwidth, useful for self-driving cars and other cases such as artificial intelligence, machine learning, virtual reality (VR) and 4K displays. FPGAs, containing physical layer (PHY)
IP to interface with GDDR6, are now emerging. Given the high data speeds involved, signal integrity is critical. This calls for careful design of the PHY for off-chip signalling, avoiding the usual hazards such as cross talk and insertion loss. Vendors of high-performance FPGAs can save time and effort by implementing proven IP such as the Rambus GDDR6 PHY. This implements the two GDDR6 16-bit data channels, and adds clock, power-management, command, address and calibration functions, implemented in 7nm process technology and advanced FinFET nodes.
OPTIMAL NETWORK CONNECTIONS Similar data-throughput challenges are being experienced with interfaces in next-generation networking and hyperscale data-centre applications. Rambus has a multi-protocol SerDes PHY capable of supporting up to four duplex lanes and data rates, from 10.3Gbps to 106Gbps, across copper and backplane channels, with more than 35dB insertion loss. Firmware-controlled PMA configuration, initialisation and adaptation provide flexibility and ease of integration in FPGA silicon. It is equally suitable for top-of-rack connections to 100/400/800Gb Ethernet networks, or for chip-to-chip (C2C) and chip- to-module (C2M) applications over connections such as the upcoming PCIe5 in 2020.
Frank Ferro, senior director, product marketing, IP cores, Rambus
MOVING FORWARD WITH MEMORY Big data and compute trends, such as AI and machine learning, are changing the industry. High-performance FPGAs created specifically to satisfy the need for accelerated, adaptable computing are demanding comparable advancements in storage and memory throughput. The latest graphics memories, such as GDDR6, present a viable solution, ready to meet future pressures. Proper implementation of off-chip interfaces is critical to ensuring the best possible performance. While leveraging proven IP is an important part of the equation, optimal routing and packaging are critical for guaranteeing maximum signal integrity at multi-gigabit speeds.
Rambus
www.rambus.com
/ ELECTRONICS
UP TO SPEED Memory, networks and FPGA
Compute Accelerators
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