Calibration Figure 2. AD7606 input protection clamp profile.
The first solution may achieve the greatest accuracy, but requires a long production test time, which largely increases a product’s cost. The second solution, although cheaper, is less accurate because it relies on the ADC’s typical input impedance and implies using controller resources, which in some cases may be limited. Alternatively, so both complications are avoided, a customer may request a larger and larger input impedance, in which case the error introduced by the front-end resistors decreases and the resulting system accuracy improves. With this approach, the problem shifts from a system problem to an IC problem. However, it may not be the most efficient method because increasing the input impedance means having to develop new solutions, which takes time and causes new problems such as higher noise due to those larger on-chip resistors. The AD7606B and AD7606C include an on-chip gain calibration feature that removes the system gain error introduced by the external resistors, achieving the greatest accuracy without having to perform any calibration, and so adding no extra cost to the system solution.
Gain Error
Figure 3. AD7606 internal PGA. Only the ±10V range is shown as an example.
The gain of the PGA is set by the feedback resistor (RFB), which is programmable to set the analogue input range, and the input impedance (RIN), which is fixed and typically 1MΩ. These resistors are trimmed to properly set the PGA gain, to scale the ±10V or ±5V analogue input signal (AIN+/-) down to the ADC input range that is, ±4.4V, as shown in Figure 3.
about –3% gain error, as shown in Figure 5. We can calculate the gain error as a function of
RFILTER by:
For easy evaluation, Equation 5 can be presented graphically as a system gain error, in % of full scale (FS) vs. RFILTER, as shown in Figure 6.
THE AD7606B/AD7606C GENERATION Within the AD7606B project development, the three products defined have input impedances and resolutions as shown in Table 1.
In either case, whether the RIN is 5MΩ or 1.2MΩ, the larger the series resistor (RFILTER), the lower the system gain - that is, the more the gain
error increases. However, the larger the RIN, the less impact the RFILTER causes, as shown in Equation 5. Theoretically, for resistors as large as 50kΩ, the
system gain error reduces from almost 5% to 1%. The comparison between both 5MΩ and 1MΩ input impedance devices in Figure 8 shows the impact on system gain error.
In some applications, that gain error can be tolerated. Such low error removes the previous need for system calibration, which was the target when designing the PGA with higher input impedance. However, in some other applications, 1% system gain error may still exceed the requirements dictated by either the industry standard or customer, so calibration may be needed anyway.
Figure 4. A series resistor in front of the AD7606’s
analogue inputs (VX+ and VX-) modifies the system gain.
than the AD7606’s gain error. Such system gain error is a concern for system designers because it means they have to perform system gain calibration themselves, such that their final product meets the accuracy target dictated by either the standards or end users. That system gain calibration can be done in two ways:
Performing a gain calibration in production - that is, passing every manufactured system through a calibration routine, storing the calibration coefficients, and using them to remove the gain errors. This is like what the ADC does at an IC level, but at a system level.
Applying a fixed correction factor to each ADC sample. As the systematic gain error is well understood per the analysis given in the following section, the digital host controller could multiply each sample obtained from the ADC by a factor that removes the system gain error. This is referred to later as back-end calibration.
However, when a series resistor is placed in front
of the PGA - let us call it RFILTER - its gain is modified from the ideal. That resistor is indeed modifying the denominator of Equation 3; therefore, the system gain is lower than what it is trimmed for.
BACK-END CALIBRATION VS. ON-CHIP CALIBRATION
Traditional calibration occurs during system factory test. The process is to:
Connect a zero-scale (ZS) input and measure the offset error.
For example, if a 30kΩ resistor is used in front of the AD7606, a 10V input signal is no longer a 10V signal at the ADC output because the AD7606’s PGA output is no longer 4.4V. The PGA output will be 4.2718V instead, as we can see if we plot the new theoretical system gain transfer function - that is,
Remove the offset.
Connect a full-scale (FS) input and measure the gain error.
Remove the gain error.
TABLE 1. AD7606B PROJECT GENERICS, TYPICAL INPUT IMPEDANCES, AND RESOLUTION
Generic AD7606B AD7606C-16 AD7606C-18 Typical Input Impedance 5MΩ 1.2MΩ 1.2MΩ Resolution 16 bits 16 bits 18 bits Continued on page 60... Instrumentation Monthly June 2026 59
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