COVER STORY
Digital power innovations overcome data centre thermal challenges
Heat generated during power conversion, particularly in power supplies over 100W, is one of the greatest challenges facing data centre and telecom network facilities. As wasted energy, this heat not only represents financial loss but also imposes further unwanted cooling costs to ensure the safe removal of waste heat and improved system reliability. In this article, Jian Yin, Intersil Corporation, talks about new power modules enabled with packaging technologies that generate less heat under all operating conditions, and provide efficient thermal dissipation which can effectively address both aspects of this issue
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asted heat is one of a number of issues that power-supply designers must deal with. The
latest generations of on-board microprocessors and FPGAs demand increased peak current, fast load transient response, and multiple supply rails including a core voltage of 1.0V or less. This dictates the close placement of point-of-load (POL) converters that can deliver a fast dynamic response without needing large numbers of decoupling capacitors that otherwise consume precious board real-estate. Digital power conversion can enhance energy efficiency, but not all modules on the market today take full advantage of digital techniques to maximise transient performance. In addition, improvements in package technology and internal component positioning are needed to minimise reliance on bulky and expensive heatsinks.
Maximising digital power advantages Compared to conventional analog designs, digital power converters can operate at high efficiency across a wider range of load conditions by taking advantage of adaptable features such as dynamic voltage scaling and frequency shifting.
Implementing the PWM, loop control and feedback digitally offers the advantages of maintaining stability without suffering the lack of responsiveness typically experienced with analog control. This allows the output capacitance required for handling transient load events to be significantly reduced, saving board real estate and bill of material costs.
Although digital control offers advantages in the fast loop design, many manufacturers are not taking full advantage of what the technology offers
Figure 1b - Digital compensation using fast sampling and FIR ripple filter with dual-edge modulator
and have simply implemented the core analog PWM techniques in digital form. Digital control makes it possible to build far more flexible control loops by incorporating n x FSW (switching frequency) oversampling, multi-rate sampling, various types of digital filters for notching and phase shaping, and Fourier transform. These features associated with complex digital signal processing are often not feasible with traditional analog control techniques. Figure 1 compares the control blocks
for Type III analog compensation typically used by voltage-mode controlled buck converters in the market today, against a digital architecture optimised for fast response. Typically, the core of a Type III compensator is a transfer function with
two zeros and three poles. The first pole near origin forms a high gain at low frequency for steady state regulation, while the second pole compensates the output capacitor ESR zero. The third pole increases attenuation of the high- frequency noises caused by switching ripples. Meanwhile, the two zeroes are used to shape the loop gain at crossover and boost phase to make the loop stable. Figure 1a shows the third pole separating from the rest of the Type III compensator. The one-pole low pass filter removes the switching ripple noises from the PWM modulator to maintain stability. However, on the other side, it inevitably introduces extra phase lag to the loop, limiting the loop bandwidth and response speed in order to have sufficient phase margin. The only way to achieve
Figure 1a - Type III analog compensation with leading-edge modulator 10 June 2016 Components in Electronics
Figure 2a - ISL8273M transient response (0 to 25A, >200A/us slew rate)
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