EDA
High-speed design and XSignals - pushing the boundaries of electrical engineering
As any engineer can attest, keeping pace with technology that is constantly evolving means mastering new tools, perfecting new methods, and improvising where necessary. With that said, high-speed design in particular could be one of the most challenging aspects of engineering that PCB designers face today. While there are many misconceptions surrounding high-speed design and its determining factors, high speed is the subsequent outcome of rise time, impedance control with PCB stack- up, trace width, and terminations. When combined, these elements allow for faster switching speeds at a high velocity. While high-speed design presents vast opportunities where technology is concerned, it also presents unique challenges for engineers tasked with bringing these concepts to fruition. Michael Doyon, senior field application engineer, Altium, tells us more
Roadblocks of high-speed PCB design
R Routing for high speed
outing specifically for high speed, depending on the approach, can either strengthen or diminish signal
integrity. So how is signal integrity reinforced by proper routing and what tools help reduce signal interference? One technique is to apply a routing topology, which promotes pin-to-pin connectivity. This minimises reflections and reinforces signal integrity. Daisy chains, for example, are a popular method used in reducing signal reflections, in addition to star topology, which is typically used for ground nets.
Maintaining timing integrity Timing integrity is also important when designing for high speed, and applications like DDRx and SDRAM designs have become standard practice. To date, these types of designs contain one or more of the following; DDR, DDR2, DDR3, or DDR4. Typically, DDR2 and in some instances DDR3 can utilise “balanced-T” or “brand
matched” topology, with DDR3 and DDR4 employing “fly-by” topology. “Fly-by” topology is a much simpler routing option, as signals are routed sequentially from one SDRAM to the next, significantly reducing signal reflections.
Establishing data lines Situating the data lines presents another common challenge. Data lines must be positioned so that they are tuned in parallel to a target length, plus or minus a tolerance. This can prove especially difficult as these lines must pass through termination resistors and multiple vias between the starting pad and final destination pads. Additionally, engineers should take into account the individual pin delays that are built into each component from the pad to subtract, which also plays a critical role in establishing viable lines.
Previous methods
In the past, engineers had no other option than to log and track every aspect of their design in spreadsheets. At the time, this was the most practical method for tracking
Image 2: Pin/Package distances can be specified as an attributes of the component’s schematic symbol (reference image: Samsung)
16 July/August 2017 Components in Electronics
Image 1: ADDR15 xSignal consists one source pin (left) connected to two destinations pins forming two unique paths
each individual segment length for nets, via depths, resistor lengths, and pin lengths. Once each component was situated in a given net and signal length was added accordingly, only then could assorted net lengths be equalised. Lucky for us, we’ve come a long way from the antiquated, fallible practices of yesterday. Advancements in high-speed routing have paved the way for much more efficient processes, eliminating the need for manual, cumbersome methods. Something engineers today can be thankful for.
Out with the old, in with the new One progressive step forward in high- speed design is the introduction of XSignals. An XSignal, simply put, is a designer-defined signal path between two nodes. These nodes can be situated in the same net, or reside in correlated nets that are separated by a component. Once the nodes are established, the XSignal can be used to scope relevant design rules that must be obeyed during interactive length tuning and various other tasks. XSignals are used to: ●Control timing by matching routed lengths
●Combine nets into a logical path ●Ignore intermediate passives ●Break continuous nets into physical subnets
●Support both balanced-T and fly-by topologies
●Ensure matching lengths during the interactive tuning process
●Implement differential pair length tuning ●Support length tuning across terminators
Pin-package delay management High-speed designs that exceed 500 MHz will typically incur a signal delay in the connection medium, most commonly referred to as a pin-package delay. Pin- package lengths are an attribute of the schematic component pin. Once length value is transferred to the PCB layout, it becomes the pin-package length of the footprint pad and is automatically included in signal length estimations. As engineers design for high speed, it's imperative that pin-package delays are accounted for when determining trace-length and package flight time.
Looking Ahead There’s no question that high-speed design has evolved significantly over the past few years, and recent advancements have made this process more efficient than ever before. Nevertheless, every step forward has it’s own unique learning curve, and engineers are first in line when it comes to sorting these obstacles out. Change is inevitable, and high-speed technology is no exception. Fortunately, there are resources that engineers can use to guide them through this process, help them acquire the necessary tools, and better prepare themselves for tackling their next high- speed design.
www.altium.com www.cieonline.co.uk
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