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VCSELs on silicon CMOS, mainly in a free space manner, but also using waveguides. ‘It’s really when you start implementing electronics on the chips to make them more powerful in terms of their capabilities, that’s when you run into the problems of the electronics generating too much heat,’ Deppe continued. ‘In addition, the applications that these silicon photonics chips are being used for also generate a lot of heat, where the chips are packed densely with a lot of other packages. The thermal barriers are quite large in terms of what kinds of laser can actually work for this.’ Deppe believes that VCSELs are the best option to overcome the thermal barriers for efficient laser operation. VCSELs have good temperature performance and, according to Deppe, CREOL has the best temperature performance of any VCSELs. VCSELs also have extremely fast modulation.

Reaching a mass market Professor Reed at the University of Southampton is leading a research project that is looking at some of the challenges in bringing silicon photonics to a mass market. The group was awarded a £6 million grant by the Engineering and Physical Sciences Research Council (EPSRC) in the UK, with the project beginning at the start of 2014. The project will investigate five areas, which were chosen, according to Reed, because they were areas that are crucial for commercialisation, yet have been less intensively investigated because most of the work has been focused on improving the performance of the technology. Consequently these are also areas where the group felt it could make a big impact in the field.

The first area is looking at low-cost methods of integrating lasers on a chip with other photonic devices, although Reed emphasised that this won’t encompass making a silicon laser. Secondly, it will investigate integrating modulators and increasing the aggregate data rate of optical transmission chips. The group is working in collaboration with Sharp to produce a chip for future generations of HD TVs, and with Oclaro for very high aggregate data rate photonic circuits. The third area is developing multiple photonic layers within a silicon chip – two or more layers, Reed specified – to improve


Cross-sectional view of an IBM silicon nanophotonics chip The group has

demonstrated a potential solution to this problem, by forming an erasable grating to couple into the circuit

the functionality. ‘You could produce layers that have different optical characteristics and also, with two layers, you could double the functionality, and perhaps you might do better than that because these layers could interact with each other,’ he explained. The fourth area is developing wafer-scale testing for a silicon photonics chip, with which the group has already had success. This is more difficult to do optically than electronically – probing electronically is, in principle, relatively simple, because there just needs to be an electrical contact. Optically, it’s more difficult because the light has to be coupled in and out, so any probing point created in the middle of a circuit to test

just one component would also be a loss point for the light after testing is complete. In this area, the group are collaborating with industry partner Wentworth Technologies. The group has demonstrated a potential solution to this problem, by forming an erasable grating to couple into the circuit. ‘We’ve found a way of changing the refractive index in a periodic way that we can subsequently erase,’ Reed said. That means a probing point could be introduced to test the

circuit, and then erased afterwards by local laser annealing. The final area will be to investigate how to align silicon photonic waveguides, which are sub-micrometre in size, with optical fibres that typically have a core diameter in the order of 10µm, and to do this in a passive way. To have a mass production technology, there has to be passive alignment, noted Reed. This is something IBM is also working on, taking the approach of integrating grating structures in the silicon in order to couple light from the waveguide to the fibre.

In addition to this grating coupling

approach, IBM is also working on a method to scale up the whole packaging design to integrate many input and output optical signals on the silicon chip. The company also wants to do that, in the longer term, over a broad wavelength range. In a paper published in 2013, IBM demonstrated one potential concept to do this, which is based upon integrating a short stretch of polymeric waveguide technology, around 1cm in length, in between the fibre and the silicon chip. The polymeric waveguide converts the very small modal field size – the very tight confinement of light in the silicon waveguide – to something that can be easily coupled to a fibre. In addition, such a concept can be scaled up to a larger number of inputs and outputs.

@electrooptics |


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