Power Management
Figure 2: When transitioning between PS1 & PS0 Modes, in response to 16A to 147A Load Steps (lite blue) at 450A/uS, Vcore (dark blue trace) deviates by ±112mV
headroom provides the ability to do power conversion within the safe operating area, design engineers do need to consider the peak current. Peak current can stress the power conversion stage as the limit of SOA is approached. The limit of the switching device should be carefully considered and the engineer needs to work closely with the PWM IC supplier in determining the overall regulation design.
In addition to the SOA of switching devices, the design parameter of low inductance inductors with increased cross
Putting all these in perspective, a VRD solution requirement may increase the needed board area. This is to
accommodate highly intelligent switching devices with accurate current sense in order to implement the new VR requirements. Of course this goes against the requirement to reserve an increasing area of board space for the microprocessor itself.
Engineers need to look for switching device companies that are closely working with controller suppliers. For example, TI and IR both have VR
Figure 3: Thermal IR image shows side view of VRM, displaying NTC Thermistor temperature with respect to Power-Stage temperature to determine VR_HOT# set-point
section area is expected to maintain reasonable inductance during a transient condition. With the limits of an inductor current sense approach it could present a potential serious problem to determine accurately the output current at the switch node. Some switching FET suppliers are developing a Sense FET approach to help resolve accurate switch node current since the increase in instantaneous current makes the inductor current sense become difficult. As the constraint for transient response in a classic feedback loop control makes it more difficult to maintain the load line, the control of the power PWM IC to provide communication with the processor is increasingly important. This is to anticipate the expected load current requirement in a feed-forward error correct approach so that it can meet the specifications for dynamic load transients.
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solutions as well as FET switching solutions. These are examples of new developments that major suppliers are working towards in order to create innovative strategic advantage over others.
A risk adverse approach to meeting voltage regulation requirements is by using a power module from a manufacturer that supplies products that comply with Intel’s requirements. Murata for example provides VRM products that not only meet the technical specifications of Intel VR12 but provide the additional benefits of increased power density, and thermal derating performance.
Murata Power Solutions |
www.murata-ps.com
William Smith is Director of Marketing at Murata Power Solutions
Components in Electronics March 2013 27
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