Power Management
Reducing losses across all load conditions
William Smith looks at how design engineers can meet the design challenges associated with delivering "green" power to embedded applications
T
he need to deliver highly efficient power to computer processing and data storage applications is becoming
even more stringent. No longer is it necessary just to deliver highly efficient power conversion. High performance embedded processor manufacturers are stipulating greater attention to phase shedding, light load efficiency and an even tighter response to transients. As processor package size reduces and
new processor products are brought to market, the leading vendors are locked in a battle for market share, where the power consumption of the end system will become a major determining factor. This is particularly the case for power saving initiatives with an improved transient response that are factored into an optimised computing power solution. Low voltage and higher current demands are challenging leading power management IC device companies to make a new definition for voltage regulation (VR). Digital control of power is seen as one of the key criteria for success and the need to intelligently control the source only extends the challenges for design engineers when tasked with creating power sources for these applications. Intel, for example, has specified the power their devices require for some time. The latest version of Intel’s power architecture, VR 12, was introduced at the end of 2011. For Murata Power Solutions, it marked the first time that an analogue controller was replaced by a digital controller for Intel's Voltage Regulator Module (VRM) applications, and the specification clearly points to the benefits of using power modules over a discrete approach.
Energy saving
The VR 12.0 specification puts emphasis on the need to reduce energy losses within the power conversion process. A key aspect of that is the need to reduce losses across all load conditions rather than just at a particular load point. One of the challenges is reducing losses during the near idle state. The use of
26 March 2013
phase shedding techniques in multi-phase regulator applications is often used to optimise light-load performance. The concept involves turning off phases thereby saving switching FET power consumption and any associated losses. The approach of phase shedding for light loads might appear simple but care must be taken in how it is implemented so it does not impact other load conditions. Its implementation requires a control loop in order to support stability of loop compensation, and the introduction of a discontinuous mode as part of loop stability. This is an area where implementation of non-linear digital control is used to manage multi-mode operation. Not using a phase will reduce energy consumption during that phase but when in switching phase, additional loss minimisation can take place. Switching off a phase may be made
possible by the use of diode emulation mode. The approach to diode emulation mode during very light loads involves turning off the lower switching FET. Adaptive dead-time control is used to
reduce the time delay needed during the switching of the upper FET switch turn off and before turning on the lower FET switch to prevent shoot through. It is a well known technique in synchronous switching converter design to reduce switching losses. The impact of gate drive voltages on switching losses are a consideration. The higher the driving voltage, the lower the turn on time of the FET, providing the ability to optimise the gate driver to achieve optimal efficiency.
Transient response
In accommodating the needs for higher performance lower loss voltage regulation, the move was made many years ago to
integrate both the switches and the drivers as a single package. This was documented as the driver MOSFET or DrMOS Power Switch specification by Intel in 2004. Widely used on voltage regulator down (VRD) solutions, an integrated driver with upper and lower FET in one package occupies less board space area compared with the discrete design approach. For example, Texas Instruments’ package solution of upper and lower FETs in a stacked die with integrated driver shows the additional benefit of a higher switching speed without the penalty of switching losses when a different FET technology are used. Prior to Intel’s VR12 specification, the output current variance from an average output current to a peak current demand was in the order of 30 to 40 percent additional current. Balancing average current efficiency and peak current demand/ transient response require optimal selection of inductor value. Generally using as high an inductance value as possible achieves the highest possible power conversion efficiency with reduced high speed transient response. A lower inductance allows faster transient response but with an efficiency reduction. Clearly, with VR 12.0, this trade-off decision has now become even more difficult.
Figure 1: In PS1 Mode, Vcore (blue trace) deviates by 20mV in response to a 4A to 20A to 4A Load Steps (green Trace) at 450A/uS
Components in Electronics
While we wait for Intel’s VR12.5 specification to be finalised, we are anticipating that key parameter criteria such as having a transient current load approaching 100% of nominal current will pose some serious design challenges for the PWM IC designer. Transient balances between phases in addition to maintaining a safe operating area (SOA) of switching device are crucial. The SOA requires an intelligent load current balance technique to prevent any one phase going beyond the desired current limit during a surge. This may well turn out to be beyond the average current mode control we have available on many multiphase POL implementations’ today. While instantaneous temperature rises may not be an issue, since thermal
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