generic manufacturing
complete device. He can then optimize it for better functionality or for better robustness with respect to fabrication technology tolerances.
Once a satisfactory design has been created in the circuit design tool, it can be transferred, via the PDA framework, to the mask layout software [4]. The user specifies a chip type available in the foundry and (if packaging options are available) a package. Such a combination of chip type and package defines the locations of the optical and electrical input and output ports.
In the mask layout software the designer can adjust the exact layout of his design to optimize for space constraints and to make sure all connections (both optical and RF or DC electrical connections) are correct.
Figure 2: Photonics Design Automation as central pivot point in the supply chain
the physical simulation software, or query a building block directly, in order to quickly simulate the response of a device. Furthermore, it can call the mask layout software to export the circuit design into a physical mask layout.
Since building blocks of one foundry can be similar to those of other foundries, many designs will be transferable from one foundry to another with only minor changes to the layout (due to differences in BB sizes and port locations), however with significant changes to the mask layers (due to differences in technologies and process flows).
Design flow
A designer of a PIC (Photonic Integrated Circuit), who wants to have his design realized by a foundry, typically starts his design by modelling it in a circuit simulator [1]. In the circuit simulator, one designs an optical circuit by placing building blocks from the foundry library with their properties into the circuit layout. The designer does not focus on how exactly a building block is implemented; the foundry rather specifies the input / output ports and, possibly in conjunction with physical layer simulators [2, 3], the wavelength dependent scattering matrix (S-matrix) of the block. By clicking together a circuit and specifying its input and outputs, the designer can very quickly calculate the spectral response of the
In the layout environment, the designer might only be allowed to see the outline of the foundry-defined building blocks. A foundry can protect its IP by just exposing a bounding box and the locations and dimensions of access waveguides and connections for electrical signals, as shown by the private building blocks in Figure 3.
When the designer is satisfied with his mask layout, he exports it to a mask file. This process involves automatic post processing on the mask layers that are defined by the foundry; for example, a waveguide on the final mask might have to be a little wider than designed to correct for under etch, or a final mask layer might have to be a local inversion of the designed waveguide.
During this foundry specific automatic mask export process, the software performs design rule checks (DRC) on both the logical and mask layer levels. An example of a logical check is the radius of curvature of a waveguide, while an example of a mask layer check is whether a metallization layer and a waveguide layer overlap – or are closer than a given distance to each other.
Since the designer has no knowledge of the inner workings of a private building block, the mask files that are produced will be incomplete as the IP- protected building blocks are left open. The export process also generates a list of the used building blocks and their exact locations in the layout.
When the foundry receives designs created with the developed design environment, for example for a Multi Project Wafer run, it assembles all the mask files from the users into one reticle or mask set.
Figure 3: Mask
design with bounding boxes for IP licensed building blocks
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Furthermore, it uses the building block information supplied by the users to fill in the private building blocks in all designs with its own proprietary mask
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