test techniques
Making Ring Oscillator Measurements
In the world of CMOS wafer parametric testing, the ring oscillator is one of the more important test structures because its test data helps confirm that logic gates are meeting their speed design criteria.Dave Rose, Senior Staff Engineer, Keithley Instruments, Inc discusses techniques for testing these devices using automated parametric testers.
A
Figure
1.Schematic (a) and block diagram (b)
representation of a CMOS ring oscillator (without trigger or buffer stage)
growing number of semiconductor fabs are incorporating ring oscillators into their overall process control monitoring test structures. Frequency measurements on ring oscillator structures are used to determine gate propagation delay, one of the critical parameters that determine how quickly a digital circuit can operate. Every logic gate has input capacitance, so no device can switch instantaneously because the input capacitance limits the speed at which a gate can switch. However, this gate propagation delay is too short for most test equipment to measure directly, so test systems measure oscillation
frequency instead and the gate propagation delay is calculated from this frequency measurement. In a CMOS fabrication process, a ring oscillator test structure is typically designed and constructed with an odd number of inverter stages. Rather than cell libraries or gates, a ring oscillator test structure is usually constructed from transistors in order to ensure an accurate representation of the parameters of interest.
The structure is designed to be as compact as possible to ensure that its performance is dominated by the transistors rather than by the interconnects. The device channel length of the transistors is usually the minimum length that the process design rules will support.
Figure 1a is a high-level schematic view of a typical ring oscillator circuit; Figure 1b is a block diagram of a ring oscillator.
The ring oscillator shown in Figure 1a (like all ring oscillators) consists of an odd number of inverter stages. The input can consist of a 2-input NAND gate that can serve as an externally controlled trigger. Once triggered, the ring oscillator will free- run at a frequency that’s dependent on the propagation delay between the stages.
Because the ring oscillator will natively oscillate at a frequency much higher than a typical parametric test system can measure directly, the output of the test structure is usually isolated with a buffer (in order to deal with the effects of test system capacitance) and its output signal divided using a
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www.siliconsemiconductor.net Issue IV 2012
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