packaging chips
Vacuum pump selection for advanced chip packaging
Today, advanced semiconductor packaging techniques are employed that move beyond simple wire bonding of a single die. Stacked dies, flip chips, and recently, more frequent employment of redistribution layer (RDL) wiring are commonplace to convert nanometer scale dimensions to ones more easily measured in fractions of a millimeter. Michael S. Boger, Global Market Sector Manager for Edwards, discusses.
W
ith greater complexity in packaging, the number of bonding
pads has, likewise, increased significantly. Further complexity is added with the introduction of interposers to act as a virtual breadboard for multiple dies in a single package – colloquially, a 2.5D device. In a few years, true 3D will be a reality with the stacking of homogeneous or heterogeneous dies. The trend to increasing complexity and 3D processing can be considered one of the “More than Moore” trends referenced in the International Technology Roadmap for Semiconductors. This trend is shown pictorially in Figure 1.
Growing challenges due to packaging topology selection are associated with greater use of vacuum-based processing tools. For example, flip-
chip packaging can make use of physical vapor deposition (PVD) vacuum processing equipment to deposit the under-bump metals (UBM) used as the bonding locations for the solder bumps.
When RDL wiring, which can also be deposited via PVD or electrochemical deposition, is added, dielectric deposition is required to insulate the metal traces. This dielectric could be chosen from a number of different materials. In particular, polyimide appears to find some level of popularity.
If, as forecasted, silicon interposers find more use in advanced packaging, a full suite of interconnect– producing, vacuum-based processing equipment will be required to create the package-enabling through-silicon-vias (TSVs) and dual-Damascene wiring (depending on the number of wiring levels).
Issue IV 2012
www.siliconsemiconductor.net 19
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