technology III-V MOSFETs current of 1170 µA/µm and a sub-threshold swing of 150 mV/decade.
These devices have several promising attributes for making an impact on the ITRS roadmap. Reductions in gate length result in an increase in current and transconductance, and the transistors appear to be immune from short channel effects. What’s more, reductions in the dimensions of the nanowire channels lead to a hike in current flow, thanks to quantum confinement.
Recently, Ye has had a paper accepted for publication in Electronics Letters that details these findings. He and his team found that the current increased by 40 percent when nanowire widths were reduced from 50 nm to 30 nm, while mobility and transconductance increased by 34 percent and just over 20 percent, respectively.
To understand why thinning of the nanowires has lead to an increase in current – this is the opposite of what one would expect – the team simulated device behaviour using Sentaurus Device, a tool made by Synopsys. Simulations revealed that nanowires operate in the volume inversion regime, which means that the electron density reduces at the edges of the nanowire and increases in its inner region. Electrons can then, on average, travel faster through the channel because it is increasingly likely that these chage carriers are away from the interface, where scattering impedes progress. Simulations suggest that the proportion of electrons in the middle of the wire increases as its dimensions are reduced, with a very promising electron density profile reached for a width of 10 nm.
Building on silicon If compound semiconductor MOSFETs are to move into production, they must be made on large diameter silicon
Figure
6.Researchers at imec are developing processes to unite germanium and III-V transistors on a silicon substrate
substrates. Forming high quality germanium and III-V transistors on silicon is tricky, due to differences in lattice constants and crystal structures, but progress in this direction is being made by Matty Caymax’s group at imec, Belgium. At CS Europe Caymax detailed efforts to form high-quality germanium and III-V devices on silicon, the latter achieved using trenches with a cup-shaped bottom (more details can be found at imec prepares the ground for III-V transistors on silicon, Compound Semiconductor March 2011 p.12). This approach (see Figure 6) eliminates anti-phase domains that lead to device shorting. “The best result that we have right now is a defect density of 2 x 108
cm-2 ,” said Caymax.
“This is not sufficient – we have to work to get a lower dislocation density.”
Transistors made recently suffer from a high junction leakage. To investigate the origin of this leakage, the team have carried out atom probe tomography, a technique that has revealed that some atoms are located in places where they should not be: Some germanium is found in InP, and some indium and phosphorous atoms are located in germanium and the underlying silicon substrate.
Figure 5. Peide Ye’s group at Purdue University have pioneered the III-V gate-all-around
FET.Transistors that they have built so far feature a gate length of 50-120 nm,a fin width of either 30 nm or 50 nm,and 1,4,9 or 19 parallel wires with a length of 150-200 nm and an Al2
O3 a thickness of 10 nm dielectric with
Caymax’s team, like those headed by Ye and Thayne, still has work to do to help III-Vs to make an impact in future logic applications. But the results to date are promising, showing ways to overcome many tough hurdles, and it seems that when silicon CMOS finally runs out of steam in a few years’ time, compound semiconductors will be there to pick up the pieces.
© 2012 Angel Business Communications. Permission required.
Issue 2 2012
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