technology III-V MOSFETs
‘Traditional’ approaches will not succeed – experiments and simulations reveal that contact resistance rises rapidly when the contact size enters the nanoscale. Several groups have recently developed different approaches for overcoming this problem, including that from Glasgow, which has turned to NiInAs to fabricate an ultra-low resistance, shallow, metallic source-drain. According to Thayne, this is the first source-drain technology that can meet the most aggressive ITRS specification for the 12 nm technology node, which corresponds to a gate pitch of 27 nm.
The third strand of research at the Nanoelectronics Research Centre is the development of approaches for forming fully self- aligned III-V MOSFETs with silicon compatible process flows. The team has pioneered two different designs: ‘Gate first’ and ‘replacement gate’ architectures. The former has been used to form In0.3
Ga0.7
Figure 3.A sulphidation process developed by researchers at the Tyndall Institute can offset most of the degradation in mobility resulting from the removal of an arsenic cap. This is a promising result for non-planar transistors,which will not have pristine interfaces
Intel’s move from planar transistors to three-dimensional varaints points the way to production of non-planar devices, which will not have pristine interfaces. To consider the implications of this trend, Thayne, in partnership with Paul McIntyre at Stanford and Paul Hurley at the Tyndall Institute, has looked at the impact of various treatments of transistor performance.
The team compared three wafers. Two of them were removed from the MBE chamber after the growth of III-V materials: A gate dielectric was added to one wafer without any intermediate surface treatment, so air-exposed oxides were likely to be present in the dielectric-semiconductor interface; and a optimised sulphidation treatment was applied to the other prior to deposition of the high-k dielectric. The third wafer had as arsenic cap deposited in the MBE chamber to prevent oxidation in air. This cap was removed in the atomic layer deposition tool at Stanford, enabling the gate deposition on a pristine surface. Measurements of the mobility of MOSFETs made from these wafers reveals that it is possible to produce interfaces as good as those on pristine surfaces if a sulphidation process is performed (see Figure 3).
The second issue that Thayne and his co-workers have investigated is the fabrication of low resistance source and drain contacts with dimensions of just a few nanometres. The ITRS roadmap dictates that as gate pitch is reduced from 75 nm in 2011 to just 15 nm in 2024, source and drain contacts must be trimmed from 21 nm to 2 nm, while source and drain resistances are cut from 160 Ωµm to 110 Ωµm.
As flatband MOSFETs with a GaO/GaGdO dielectric stack and a 100 nm gate length. These transistors exhibit a peak drain current of 250 µA/µm, transconductance of 150 µS/µm and a sub-threshold swing of 150 mV/decade. Sub-threshold swing falls to 130 mV/decade with the replacement gate architecture, which has a modest on-state performance due to a very high access resistance of 18 kΩµm. This issue can be addressed by improving the source drain anneal, which is needed to supress material diffusion in very small devices.
Into the third dimension One team that is following Intel’s lead and taking III-V MOSFETs into the third-dimension is Peide Ye’s group from Purdue University. Ye detailed an evolution path for FETs, which begins with a bulk III-V planar architecture and ends with a III-V gate-all- around HFET (see Figure 4). His team have recently fabricated the latter structure, which is built on InP substrates and features a p-doped InGaAs channel, or multiple channels, wrapped in a 10 nm-thick layer of Al2
O3 and a thicker layer of WN (see Figure 5
for details). Devices with 4 parallel channels, a 50 nm gate length and a 30 nm fin width produce a very low gate leakage, a peak
Figure
4.According to Peide Ye from Purdue University,III-V MOSFETs have evolved from planar structures to those that wrap a dielectric right around the channel
The second issue that Thayne and his co-workers have investigated is
the fabrication of low resistance source and drain contacts with dimensions of just a few nanometres. The ITRS roadmap dictates that as gate pitch is reduced from 75 nm in 2011 to just 15 nm in 2024
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