Technology - Manufacturing
Other presentations during the 2-day program addressed many unique fab, tool and technology requirements for larger wafers. These presentations demonstrated that while pilot plans are sharpening, considerable work has yet to be completed
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accelerates industry consolidation.” Estimating the cost of the transition at $25 billion, Lebon said the 300 mm wafer size transition “wasn’t cost effective.” One of the ways to manage costs will be through “fewer equipment platforms.” Imec is still trying to formulate a role in 450, and claimed there “still was a long journey to go.” Tom Jefferson from SEMATECH, however, sees a clear timeline, schedule and participation process in place for 450. He stated that over 40 companies are participating in the program, defects per wafer have been reduced from more than 3000 to less than 200, and that effective SEMI standards have been developed to enable development. Jefferson reiterated the key details of the September announcement that IBM, Intel, TSMC, GlobalFoundries, and Samsung, along with the College of Nanoscale Science and Engineering, University of Albany, State University of New York, have committed $4.4 billion to next-generation chip research, including 450 mm wafer processing. How much of the announced $4.4 billion was already- committed IBM money for other (non-450) advanced chip design and technology development was not verified. The new fab site has been prepared and walls are going up on the fast-track project. Nanoimprint technology from EV Group will be used as the “stopgap measure” in lieu of a workable EUV solution. On Day 2 of the Session, Jefferson returned to clarify that the pilot line will include 50 types of tools, many with more than one supplier contributing. The goal of the pilot line will be to develop a database that will be used to support production tool purchasing. Participants in the program will benefit from access to patterned and non-patterned wafers, shared metrology and
Multi Application Carriers (MACs), shared consortium staff resources, data sharing, and “financially leveraged business partnerships” with consortium partners. Suppliers who do not participate in the program will be lower on the priority for access to test wafers. The impression left was that not participating in the program will lower the probability of participation in production line rollouts by consortium partners. Jefferson also clarified the intercept point of the pilot line. The consortium is expected to have different intercept points for logic and DRAM, but the “expectation should be for 10 nm and beyond,” and the timing for the second half of 2013-early 2014.
New Requirements for 450 Fabs Other presentations during the 2-day program addressed many unique fab, tool and technology requirements for larger wafers. These diverse presentations demonstrated that while 450 mm pilot plans are sharpening around firm schedules and requirements, considerable engineering and science work has yet to be completed. Peter Csatary, Head of Group Technologies,
M+W Group, highlighted utility, construction, material handling requirements for a 450 fab. Ines Stolberg, Manager Strategic Marketing Litho, Vistec, discussed their concept for a direct write, variable beam (rather than single beam) approach to maskless lithography. Guilhem Delpu from Recif discussed work being funded by the EU on improving vibration, cleanliness and substrate affects on wafer handling. Geert van der Zalm of Bosch Rexroth also discussed alternative material handling approaches and control strategies for 450 mm wafers to manage vibration with heavier loads and longer arms. “We may need to rethink tool architecture, such as using inverted linear motor to enable inline vacuum transport that has been proven useful in the solar industry.” Results from another European funded
project on etch process development illustrated the challenges in 450 mm process development. Mike Cooke from Oxford Instruments indicated the first tests on 450 PECVD SiO2 processing have so far yielded only a 4.2% uniformity across all points. In induction coupled etch plasma, a +/- 10% uniformity across a 450 wafer has been achieved (half of the non-uniformity at the wafer edge), that according to Cooke was “not good enough, but a useful start.”
© 2011 Angel Business Communications. Permission required.
www.euroasiasemiconductor.com Issue V 2011
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