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8 Reasons
to Work with Spire
Semiconductor
to Develop
Your Next
Optoelectronics
Product...
Fig. 5 Thermal FEA result comparison for the zero process heat load (top) and
maximum process heat load (bottom). The predicted uniformity indicates the promise of
an order of magnitude improvement relative to the baseline depicted in
spanning the aforementioned two thermal performance and long-term
geometries. These versions were funneled structural robustness.
down to a final embodiment through the However, the inverted cone provided the
Spire Semiconductor is a complete
compound semiconductor fabrication
two-stage, multi-physics finite element best overall combination of temperature
1
facility dedicated to supporting its
analysis (FEA) process depicted in Figure uniformity, stress margins and
customers.
4. manufacturability (lathe operation only
Spire Semiconductor has its own MOCVD
versus lathe and mill or weld for the III-V and II-VI multi-wafer, multi-reactor
This process was comprehensive in scope, reentrant post).
2
capabilities for high volume production
requirements.
accounting for all heat conduction paths
subjected to the process heat generation Although the results also indicated the Spire Semiconductor has a first-class
and radiation and convection boundary top weld joint might undergo significant
3
compound semiconductor device
fabrication facility with class 100
conditions established in creep deformation as the temperature
cleanrooms.
the chamber, as well as the coupled exposure time approached 10,000 hours,
inelastic thermal strains and associated the 70 percent higher yield stress limit at
Spire Semiconductor’s engineering staff
has extensive experience in material
stresses in the entire pedestal heater the 100 hour mark was large enough for
4
and device design, process development
subassembly. the inverted cone to retain adequate
and testing.
elasticity during thermal cycling intervals
You can work directly with Spire
Outcome more representative of actual use. Heating
5
Semiconductor’s engineers.
As a result of numerous FEA simulations, a wafer to achieve a surface temperature
Spire Semiconductor can manufacture
one of the originally-conceptualized versions “super-uniformity” approaching one percent
6 your products in volume exclusively
of the inverted cone geometry ultimately of the application set point temperature is
for you.
emerged as the preferred shaft redesign not trivial from the heater design
As a pure play foundry, we do not
alternative for improving the pedestal perspective. 7
compete with our customers.
heater’s uniformity.
Comprehensive, FEA informed trade
Working with Spire Semiconductor will
8
keep you ahead of your competition.
The illustrative thermal FEA result case studies accounting for coupled physics
presented in Figure 5 suggests the effects, design and manufacturing rules,
theoretical feasibility of a one percent as well as material limits are beneficial to
surface temperature uniformity goal for a achieving aggressive performance goals,
Edward D. Gagnon
General Manager,
hypothetical process scenario. The inelastic particularly when legacy components are Spire Semiconductor
thermo-mechanical FEA results verified the being considered for retrofitting into next
reentrant post was superior in terms of generation systems.
Thomas Kupiszewski is a design analysis expert with more than 23
years experience in developing and manufacturing custom electric
equipment for cryogenic and high temperature applications.
Kupiszewski holds a bachelor’s degree in Engineering and Applied
Semiconductor
Science from the California Institute of Technology and a master’s
Spire Semiconductor, LLC
degree in mechanical engineering from the University of Wisconsin-
25 Sagamore Park Road, Hudson, NH 03051
T 603.595.8900 F 603.595.0975
Madison.
sales@spiresemi.com
November / December 2009 www.compoundsemiconductor.net 33
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